Help on Type operator section in LRM

Hello Everyone,
Can someone explain how to use “type” keyword in declaring variables.

When a type reference is used in a net declaration, it shall be preceded by a net type keyword;
and when it is used in a variable declaration, it shall be preceded by the var keyword.
var type(a+b) c, d;
c = type(i+3)'(v[15:0]);

When i try to use the same code it is not working for me. First of all i didn’t understood what is the use of it.

It would help us very much if you could show a more complete example and explain what about it is not working for you. I realize this example is straight out of the LRM, but it was only intended to show syntax, not complete functionality.

The type operator is useful when you know the name of a variable but no its type, and you need the type to declare another variable or perform a cast. This can happen when you import a variable from a package, have a parameter that has been overridden with a different type, or in a macro. For example

`define swap(arg1,arg2) \
begin \
  var type(arg1) temp; \
  if (type(arg1) != type(arg2) $error(`"type of arg1 does not match arg2`") \
    else begin temp = arg1; arg1 = arg2; arg2 = temp; end \
end

In reply to dave_59:

Hi Dave,
Below code itself is failing for me with vcs/Rivera-pro. Do you see any problem with this?


int tp1,tp2;

  initial begin

    var type(tp1) tp3;
    
  end

ERROR VCP2000 “Syntax error. Unexpected token: type[_TYPE]. The ‘type’ is a SystemVerilog keyword and cannot be used as an identifier. Use -v2k5, -v2k or -v95 argument for Verilog compilation.” “testbench.sv” 8 13
ERROR VCP2000 “Syntax error. Unexpected token: tp3[_IDENTIFIER]. Expected tokens: ‘(*’ , ‘++’ , ‘–’.” “testbench.sv” 8 22
FAILURE “Compile failure 2 Errors 0 Warnings Analysis time: 0[s].”
Exit code expected: 0, received: 1

In reply to Naven8:

Works fine with ModelSim/Questa.