Help - QuestaSim can't randomize for array of union

SystemVerilog
, , ,
1

Hi,

I have an issue that can’t randomize for array of union with QuestaSim but still ok with VCS.

typedef union packed {
bit [15:0][7:0] rawdata;
prot_slot_u prot; // another union
ctl_slot_s ctl; // this is packed struct
} my_slot_u;

my_slot_u [3:0] slot;
assert(std::randomize(slot));

with above code, Questasim will " Error: Assertion error"
Warning: (vsim-7175) randomize() failed due to a non-reproducible constraint conflict.
Warning: (vsim-7084) No solutions exist which satisfy the specified constraints; randomize() failed.

If I change to std::randomize(slot) => there’re no error but my array of union “slot” will all zero.
Does questasim need keyword rand to random?
With VCS, I can randomize with above code.

Thank you.

2

In reply to xdarksadx:

It would help to show a complete runnable example. This worked for me

module top;
  typedef union packed {
    bit [31:0] b,c;
  }prot_slot_u ;
  typedef struct packed {
    bit [15:0] a,b;
  } ctl_slot_s;
  
  typedef union packed {
    bit [3:0][7:0] rawdata;
    prot_slot_u prot; // another union
    ctl_slot_s  ctl;  // this is packed struct 
} my_slot_u;

my_slot_u [3:0] slot;
  
  initial begin
    assert(std::randomize(slot));
    $displayh("%p", slot);
  end
endmodule
3

In reply to dave_59:

Thank you Dave,
I’ve tested at EDA playground with your code, the result is OK.
‘{’{rawdata:‘{21, 3b, f5, b8}, prot:’{b:213bf5b8, c:213bf5b8}, ctl:‘{a:213b, b:f5b8}}, ‘{rawdata:’{d6, 5e, 13, dd}, prot:’{b:d65e13dd, c:d65e13dd}, ctl:‘{a:d65e, b:13dd}}, ‘{rawdata:’{0c, 0a, c7, 11}, prot:’{b:0c0ac711, c:0c0ac711}, ctl:‘{a:0c0a, b:c711}}, ‘{rawdata:’{3a, dc, 34, 6c}, prot:’{b:3adc346c, c:3adc346c}, ctl:'{a:3adc, b:346c}}}

Maybe my struct or union have some conflict constrains so that Questa reported error/warning.