Help needed for an assertion question

SystemVerilog
,
1

Hi, I am trying to write an assertion for the following question.

A high for 5 cycles and B high after 4 non-continuous highs of A and finally both A and B are high.
Can you please help me write an assertion for this.

2

In reply to sruthikrapa:

If there is a clock for this particular check simple way to write this one. 

property abcheck ;
@(posedge clk) a |-> a[->4] ##0 b ##1 a ##0 b;
endproperty
3

In reply to sruthikrapa:

sequence s1;
A[=4];
endsequence

property p1;
@(posedge clk) s1 |=> [0:$] (A&&B == 1) ##1 (A||B == 0) ;
endproperty

Is this what you needed?

4

Thank you yourcheers and kddholak for your answers.
They are useful.

-Sruthi.