In reply to foxtrot:
Quote:
..but it's a vacuous pass even when ack rises after say 4 or 6 clk2 cycles.
Vacuity occurs only if the antecedent
$rose(req)==0.
Keep in mind that at every clocking event (i.e., the
@(negedge clk1)) you have an attempt at the property, and if in the cycles af$ter the successful
$rose(req) you have no more rose, then those attempts are vacuous. Maybe what you see are those vacuous threads.
However, the attempt with a successful
$rose(req) can finish in one of the possible ways:
PASS, FAIL, INCOMPLETE (if at end of simulation
ack never occurred).
Try the following
ap_reqack: assert property(@(negedge clk1) $rose(req) |->
@(posedge clk2) !ack[*4:$] ##1 ack) $display("%t PASS", $realtime);
else $display("%t FAIL", $realtime);
Ben Cohen
http://www.systemverilog.us/
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