In reply to juhi_p:
When compiling SystemVerilog files, the scoping of variables and classes is very important. Unfortunately, developers get lazy and fail to completely `include all the required files to resolve every `define or other declaration. This in turn requires an option known as 'multi file compilation units', where every file compiled is considered part of the same compilation scope, and resulting in declarations not being scoped correctly.
To ensure this doesn't occur, the recommendation is that every file can be compiled independently and not rely on any other file being compiled at the same time.
An example of this is where you see two files, defines.sv and design.sv. If the design.sv doesn't include the defines.sv file, this results in some undefined references.
The proper way is to `include defines.sv. However, developers are lazy and will instead compile both defines.sv and design.sv at the same time, requiring the compiler to carry over the defines from one file to the next. If you compile several hundred files at the same time, this can lead to some defines carrying over to other files where they aren't desired.
By including the correct files at the correct locations, you can avoid all of these issues.