Getting Issue during the run time

SystemVerilog
1

Hi,

I have written code which contains three SV files. When I include all the files in design.sv I could able to see the result but when I seperate the files I am getting run time error. Below I am sharing the link in which I am getting the error. Please help me.

Thanks…

2

In reply to narendrareddy:

What specific error are you getting? The link you posted gives a ‘multiply defined’ error because you include the same file multiple times. If so, don’t include the file multiple times.

3

In reply to cgales:

Hi,
I am getting same ‘multiply defined’ error.I don’t know which file I have included multiple times. Please help me to remove this error.

Thanks…

4

In reply to narendrareddy:

Where do you have `include several times?

5

In reply to cgales:

I have included include "packet.sv" in generator.sv and driver.sv because I am taking the handle of packet in generator and the driver. If I don't include this I am getting the error. Please suggest me what to use instead of include in other files.

Thanks…

6

In reply to narendrareddy:

If you remove the `include line from generator.sv and driver.sv, you won’t get any compilation error.

7

In reply to cgales:
Thank you I have removed `include in the generator.sv and driver.sv the issue is solved.

I have modified the packet.sv file as shown below. This code is also solving the problem even if there is `include in generator.sv and driver.sv. I don’t have much idea on the when we use 'ifndef and 'define. Can you please tell me when to use this…

ifndef _packet__sv_ define packet__sv

class packet;
rand bit [7:0]addr;
rand bit [15:0]data;

constraint valid{
addr inside {[0:10]};
data inside {[100:200]};
}
endclass

`endif

8

In reply to narendrareddy:

Never use ifndef/define brackets. They are a poor coding practice and will lead to unintended side effects.

9

In reply to cgales:

ok!!! Thank you :)

10

In reply to cgales:
can you please tell what can be side effects of using those?

11

In reply to juhi_p:

When compiling SystemVerilog files, the scoping of variables and classes is very important. Unfortunately, developers get lazy and fail to completely include all the required files to resolve every define or other declaration. This in turn requires an option known as ‘multi file compilation units’, where every file compiled is considered part of the same compilation scope, and resulting in declarations not being scoped correctly.

To ensure this doesn’t occur, the recommendation is that every file can be compiled independently and not rely on any other file being compiled at the same time.

An example of this is where you see two files, defines.sv and design.sv. If the design.sv doesn’t include the defines.sv file, this results in some undefined references.

The proper way is to `include defines.sv. However, developers are lazy and will instead compile both defines.sv and design.sv at the same time, requiring the compiler to carry over the defines from one file to the next. If you compile several hundred files at the same time, this can lead to some defines carrying over to other files where they aren’t desired.

By including the correct files at the correct locations, you can avoid all of these issues.