Getting error in verifying the dual port ram project in system verilog

SystemVerilog
1

** Error: environment.sv(5): Invalid type ‘write_bfm’. Please check the type of the variable ‘wr_bfm’.

** Error: environment.sv(6): Invalid type ‘read_bfm’. Please check the type of the variable ‘rd_bfm’.

** Error: environment.sv(7): Invalid type ‘write_monitor’. Please check the type of the variable ‘wr_mn’.

** Error: environment.sv(8): Invalid type ‘read_monitor’. Please check the type of the variable ‘rd_mn’.

** Error: environment.sv(9): Invalid type ‘scoreboard’. Please check the type of the variable ‘score’.

** Error: environment.sv(35): Undefined variable: wr_bfm.

** Error: environment.sv(36): Undefined variable: rd_bfm.

** Error: environment.sv(37): Undefined variable: wr_mn.

** Error: environment.sv(38): Undefined variable: rd_mn.

** Error: environment.sv(39): Undefined variable: score.

** Error: INTERFACE_DPRAM.sv(1): near “interface”: syntax error, unexpected interface, expecting class

these are the errors

2

In reply to quuen kashyap:
We can’t help you with syntax errors without seeing any of your source code. If the invalid types are supposed to be classes, I hope you have defined them in a package and imported the package.

3

In reply to dave_59:

But sir I created all classes (files) nd in this file only created handle of that class but showing error plz help

4

In reply to dave_59:

We can’t help you with syntax errors without seeing any of your source code.

5

plz read this