In reply to Muneeb Ur Rehman:
There are several syntax errors.
The if/else should be inside an always block. It is better to use a case statement instead of an if/else.
Multiple statements need to be enclosed by begin/end keywords.
Don't use the assign keyword inside an always block.
It's recommended to use blocking assignments (=) for combinational logic.
This code compiles without errors:
module mini_alu #(parameter integer DATA_WIDTH = 2)
(
input logic unsigned [DATA_WIDTH-1:0] A, B,
output logic unsigned [DATA_WIDTH-1:0] C
);
//OP CODES AND THEIR FUNTION:
// 00 = A|B
// 01 = ~A
// 10 = A^B
// 11 = A&B
always @* begin
case (C)
2'b00: begin
$display ("OR OPERATION WILL BE PERFORMED %0d :", C);
C = A|B;
end
2'b11: begin
$display ("AND OPERATION WILL BE PERFORMED %0d :", C);
C = A&B;
end
2'b10: begin
$display ("XOR OPERATION WILL BE PERFORMED %0d :", C);
C = A|B;
end
2'b01: begin
$display ("NOT OPERATION WILL BE PERFORMED %0d :", C);
C = ~A;
end
default: begin
$display ("No Operation To Be Performed ");
end
endcase
end
initial begin
$dumpfile ("dump.vcd");
$dumpvars (1, mini_alu);
end
endmoduleIt is a little odd that you are checking C then assigning to C. Perhaps you intended to have another input signal, like a 2-bit mux select.
