'genvar' statement related

SystemVerilog
1

Hi,

I am using ‘genvar’ for the below code,please tell me if there is anything wrong.

The code in tb_top file:

genvar count;
generate 
  for (count=0;count<8;count++) begin:abc
    abc_if handel_if(clk);
  end
  initial begin
    uvm_config_db#(virtual abc_if)::set(null,"xgbe_static", $sformatf("abc_port_if_%0d",count), handel_if);
  end
endgenerate

generate
      for (count=0;count<8;count++) begin:def
          if(count==0) begin
              some code.....
          end
          else if(count==1)begin
              some code.....
          end
endgenerate

Doing get like below mentioned:

   for (int i=0;;i++) begin
     if( uvm_config_db#(virtual abc_if)::get(null, "xgbe_static", $sformatf("abc_port_if_%0d",i*2), abc_if0) == 0) begin
       `uvm_error(get_type_name(), $sformatf("Can NOT find eth_port_if."))
     end
2

In reply to Saikat Sana:

You could help others help you by providing more information about the problem you are facing. - i.e. what errors you are getting and what you expected to work.

The only thing I can see wrong is your initial block needs to be moved inside the for loop.

3

In reply to dave_59:

Thanks for pointing the wrong statement Dave.

4

After the correction made by Dave, still I am facing some problem.In my environment for some testcases it is selecting count no as 7. But I need count no to be 5, so that I can execute my scenario.So here my question is how(why) the second generate loop is selecting count no as 7 always? Second question is, Can I use one genvar variable for two/three generate loop(like I am using one genvar count for two generate loop in tb_top file)?

generate
for (count=0;count<8;count++) begin:def
if(count==0) begin
some code…
end
else if(count==1)begin
some code…
end
like this way till count==7 same code.
endgenerate