Generating an IO interface in a module based on parameter

SystemVerilog
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1

Is it possible to generate a list of input/output ports + instantiation in top module based on the parameter configured by user?
The top module has hierarchy:
top
– axi_slave (AXI Slave ports + control and status ports)
– core (control and status ports)

If user configures parameter AXI_SLAVE = 1:

  • The top module should only have AXI Slave ports.
  • axi_slave module should get instantiated.
  • core module should get instantiated.
  • axi_slave contain registers whose bits are taken out and mapped to control and status ports of core module.

If user configures parameter AXI_SLAVE = 0:

  • The top module should only have control and status ports(same that of core).
  • axi_slave module should NOT get instantiated.
  • core module should get instantiated but with different set of port mapping (one-to-one with top).

I wonder how this can be implemented (preferably without using interface feature of SV)…