Generate block in sv

SystemVerilog
1 
module GCounter #(parameter WIDTH = 8) (clk, rst, count, wraddr);
		
		input                 clk;
		input		      rst;
		output [WIDTH-1:0]  count;
		output [WIDTH-1:0] wraddr;
		reg    [WIDTH-1:0]   temp;
		genvar i;
		
	always@(posedge clk, posedge rst) begin
			if(rst) temp <= 0;
			else temp <= temp +1;
	end

	generate 
		for(i = 2; i < WIDTH+1; i = i+1) begin
		   	count[i-2] <= (temp[i-1] xor temp[i-2]);
		end
	endgenerate
		   
	assign count[WIDTH-1] = temp[WIDTH-1];
	assign wraddr = temp;

endmodule

the above code is showing error while running??

2

In reply to ulhaqsalman:
It helps to show the error message and the line it is pointing to.

You are getting a syntax error because you are attempting to put a simple procedural assignment statement inside a generate-for loop. Most likely you forgot the [font-courier new]assign keyword.

You can simplify this in SystemVerilog to

module GCounter #(parameter WIDTH = 8) 
(
 input 			  clk,
 input 			  rst,
 output wire [WIDTH-1:0]  count,
 output logic [WIDTH-1:0] wraddr);
   
   always @(posedge clk or rst) begin
      if(rst) wraddr <= 0;
      else wraddr <= wraddr +1;
   end
 
   generate   
      for(genvar i = 2; i < WIDTH+1; i++) begin
	 assign count[i-2] = (wraddr[i-1] ^ wraddr[i-2]);
      end
   endgenerate
   assign count[WIDTH-1] = wraddr[WIDTH-1];
 
endmodule
3

Thanku Dave