Generate for assign statement -> how to?

SystemVerilog
,
1

Hi All,

I’d like to write the following expression using a for generate loop:

`define sram_rdy(i)  sram``i.rdy
// sram_rdy
assign sram_rdy = sram7_rdy & sram6_rdy & sram5_rdy &sram4_rdy & sram3_rdy & sram2_rdy & sram1_rdy & sram0_rdy ;

How can I write the above assign statement using ‘generate for …’?

Thank you!

2

In reply to ldm_as:

https://verificationacademy.com/forums/systemverilog/combination-generate-and-macro#reply-41576

3

In reply to dave_59:

will the following work?

// macro
`define sram_rdy(i)  sram``i.rdy
// sram_rdy
genvar i;
reg tmp = sram_rdy(0);
generate for (i=1;i<8;i=i+1)
  tmp = tmp & sram_rdy(i);   
end
endgenerate
assign sram_rdy = tmp;

Is the above code synthesizable?

4

In reply to ldm_as:

No and No.

5

In reply to dave_59:

Why?

6

In reply to ldm_as:
https://verificationacademy.com/forums/systemverilog/combination-generate-and-macro#reply-41576