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  • generate 32 bits of data which will have 10% of bits (average) toggling over "n" number of transactions

generate 32 bits of data which will have 10% of bits (average) toggling over "n" number of transactions

SystemVerilog 4972
system verilog 1 constraint randomization 29
sk9
sk9
Forum Access
27 posts
November 01, 2016 at 6:21 pm

Hi all,

I am trying to generate 32 bits of data which will have 10% of bits (average) toggling over "n" number of transactions. For example, Let's say 10% of bits should toggle out of 32 bits for every N number of transactions. N can be a random variable.

I wrote the below code but was not able to write the constraint which can hep me with 10% of the bits being toggled. I am thinking to use dist. Please help me how to write the constraint for 10% of the bits getting toggled for every N number of transactions.

class data;
  rand bit [31:0] data;
  rand int unsigned N;
  constraint dist {$countones(data) dist{1:=90, 2:=10};}   
endclass
 
module toggle;
  initial begin
    data data_handle;
    data_handle = new();
 
    $display("------------------------------------");
    repeat(data_handle.N) begin
    data_handle.randomize();
      $display("\t \tdata = %032b, \ttransactions = %0d",data_handle.data, data_handle.N);
    end
  end
endmodule

Can you guys please help me with this.

Thanks in advance,
Sruthi.

Replies

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sharvil111
sharvil111
Full Access
176 posts
November 01, 2016 at 9:14 pm

In reply to sruthikrapa:

The problem statement is not very clear to me. As far as I got the issue, you can use the following constraint:

constraint dist {$countones(data) inside {[3:4]};}

Since 10% of 32 bits is 3.2, I have kept 3 to 4 bits as 1. In every randomization, 3-4 bits will be kept 1 and the subsequent randomization, some other set of bits will be set to 1. Thereby resulting in toggling of bits. You can also use dist operator as shown in the question sample as follows:

constraint dist {$countones(data) dist {3:= 70, 4:=30};}

Please elaborate if this is not your requirement.

- sharvil111 | ASIC Verification

dave_59
dave_59
Forum Moderator
8574 posts
November 01, 2016 at 11:22 pm

In reply to sharvil111:
When you say you want to toggle a bit, that is not the same as setting a bit. A toggle implies a change in state from one transaction to the next. The following constraint will, on average, toggle 3.2 bits out of 32 bits on each call to randomize().

constraint toggle_bits {$countones(data ^ const'(data)) dist {3:= 80, 4:=20};}This reads "the count of ones when you XOR the (rand data) with the (previous data) should be 3 or 4".

But if you want to spread the 10% toggles over N transactions, that is a much harder problem. Assume the case where N=100 transactions. Then you have the potential for (100-1)*32 = 3168 bit toggles, so 10% of that is 316.8 toggle. Now the question becomes, is it OK to use the above constraint (assuming you adjust the average to 3.168 bits toggled per transaction), or do you need a wider distribution of bits toggled per transaction (i.e. sometimes no bits, sometimes all bits toggling per transaction)? If so, there is no way to do that with independent randomizations.

What you can do is randomize N transaction in an array and constrain the toggles within the array.

class data_c;
   rand bit [31:0] data[];
   int P=10; // Percentage
   rand int unsigned N;
   constraint data_size {
      N inside {[1:10]};
      data.size() == N;
   }
   constraint toggles {
      data.sum() with ( $countones((item.index<N-1)*(item^data[item.index+1])) ) == (N-1)*32/P ;
   }
endclass 

— Dave Rich, Verification Architect, Siemens EDA

sharvil111
sharvil111
Full Access
176 posts
November 02, 2016 at 12:20 am

In reply to dave_59:

Yaa I agree with the XOR. As I stated earlier, I was not clear about the intent. This suggestion made it clear about distribution. Thanks for that.

I believed that first randomization will set any 3-4 bits out of 32 and the second/subsequent randomization will set some other bits. Thereby the previous bits will be reset and hence we can observe toggle of those bits. But this was a very rough idea. Your solution makes things clear.

- sharvil111 | ASIC Verification

kernalmode1
kernalmode1
Full Access
86 posts
December 26, 2018 at 12:14 pm

In reply to dave_59:

Hi Dave,

Does const' casting data always result in the previous value? Is this true for every randomization? Also, is it tool dependent or LRM compliant?

kernalmode1
kernalmode1
Full Access
86 posts
January 26, 2019 at 11:47 am

In reply to dave_59:

Ping. Anybody?

const' casting inside constraints always gives the previous value?

dave_59
dave_59
Forum Moderator
8574 posts
January 26, 2019 at 12:55 pm

In reply to kernalmode1:

See https://verificationacademy.com/forums/systemverilog/generating-random-values-increasing-order#reply-58225

— Dave Rich, Verification Architect, Siemens EDA

kernalmode1
kernalmode1
Full Access
86 posts
January 26, 2019 at 2:37 pm

In reply to dave_59:

As Jonathan Bromley says on the other post (BTW, nice to see him here in the comments), not sure if the interpretation of the sentence is done the same way by all the tool vendors. At least the available ones on edaplayground error out. Maybe works on a newer version, not sure.
I guess that is a discussion for some other day and some other place.

Thanks for the link Dave!

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