Generate a 2/3 clock frequency in TB using System Verilog and Verilog

SystemVerilog
,
1

Hi,

I came across the concept of clock generation and I am trying to understand if I can generate a clock for a let’s say a 2/3 clock divider i.e., 0.66 duty cycle using the system Verilog and Verilog. I would like to understand the difference. I am working on a pseudo-code but any other help to code would be greatly appreciated to help me understand the concept of how to generate the clock with any frequency other than the 50% duty cycle.

Thanks,
Sruthi.

2

In reply to sk7799:

At it’s most basic.

A typical 50% duty implementation:

initial begin
   clk = 0;
   forever #10 clk = ~clk;
end

Could be implemented:

initial begin
   clk = 0;
   forever begin
       #5;
       clk = 1;
       #5;
       clk = 0;
   end
end

So a 66.6% duty, is simply:

initial begin
   clk = 0;
   forever begin
      #3.333;
      clk = 1;
      #6.667;
      clk = 0;
   end
end

Then put this in an interface, embellish it with enable/disable, glitch-free frequency changes, jitter, etc.

3

In reply to warnerrs:

Hi Warnerrs,

Thank you very much for the prompt response.

If possible can you please explain the code for the 66.6% duty cycle.

Also, for 2/3 frequency, it’s 0.66 right?

Please clarify.