hi,
i read these lines. "“The commands read or write to either a memory address space or a register address space. The commands also specify whether the read or write transfers data in a linear or wrapped sequence”
-
what is register address space and linear and wrapped operation in register address space.?
-
is register address space means writing and reading from queue?
3)doubt: when we are connecting our IP with DUT, is it necesary to write modport and clocking block in interface? as per my understanding, we write clocking block to avoid race condition in IP. am i right? or is it necessary during connection between IP and DUT.
THANKS
In reply to Er. Tripathi:
hi,
i read these lines. "“The commands read or write to either a memory address space or a register address space. The commands also specify whether the read or write transfers data in a linear or wrapped sequence”
Context is important, and would help us answer your questions. Where are you quoting this from?
- what is register address space and linear and wrapped operation in register address space.?
- is register address space means writing and reading from queue?
It sounds like you could be reading an AXI spec, or similar document. We’re designing hardware with these languages and specs. A bus spec like AXI is simply describing how a transfer (or burst of transfers) can occur to an unspecified device. It’s up to the designer to determine what needs to happen when those transfers occur. The transfers could be happening to a register which controls some peripheral operation; or a communication fifo for transfer to other location; or to local storage (i.e. a DDR). It’s all up to the design.
“Wrapped” addressing usually refers to burst transfers which are intended to be limited to a certain address range - i.e. a 2KB wrapped burst could start its transfer anywhere within a certain 2KB block (of a large address range) but wrap when it hits a 2KB boundary. Memory Cache line transfers are a common use case.
I’ll leave your 3rd question for another poster.
Regards,
Mark
In reply to Mark Curry:
Modports offer little value for testbenches. There are needed for synthesis. Most testbench writers want access to everything regardless of the way the code was written, and simulation tools have gotten lax in enforcing directions.
Clocking blocks can help, but are not required to prevent race conditions between TB and DUT. Use of opposing clock edges is simple and effective. Also see
In reply to Mark Curry:
yes, i got confuse for register address space. in practical terms like developing VIP,how i code for register address space… my thought was… data is coming from transaction, and need to store in queue and then slave driver will get it through queue.? is this valid approach for register address space?