I am trying to come up with a way to model the termination on a pin.
The expectation is:
E1: When termination for the pin is turned on, without any driver, the pin should be pulled up. If the driver for the pin is present it should drive whatever the value was provided.
E2: When the termination is off, without any driver, the pin should always be high z. If the driver is provided, the pin should drive whatever the value is provided.
I specifically want to achieve this using gate level modeling.
wire term_en; // enables/disables the termination for the pin
wire a; // signal that drives the pin externally
wor o; // resolved output signals
wor w1, w2, w3, w4, w5;
// How do I go about modeling it?
// My thought process is this:
// I need an buffer that lets me drive the input as is when term_en=1
nmos n1(w1, a, term_en);
// But when term_en=0, output will be 'z, so this will not work
// For E1, I need a way to pass 0 and 1 as is, but convert z to 1.
// I tried below:
//Add a pull up
pullup (pull1) p1 (w2);
// pass through 0 and 1 but pull up z since 'z output will be pulled up by p1
// But this will have a disadvantage of pulling up the output when term_en=0
nmos n2(w2, a, term_en);
//To get an expected output, I tried to play around with w1/w2 using and/or gates to get expected output, but I end up getting output as 10x101 since and/or truth table does not result in z.
or n3(w3, w2, a);
and a1(w4, w3, term_en);
and a2(w5, a, ~term_en);
or o1(w6, w4, w5);
//term_on : 000111
//input : 10z10z
//w1 : zzz10z
//w2 : 111101
//expected: 10z101
//w6 : 10x101
Is there a better way to do it?