Functional Coverage: generate ignore bins at start of sim

Question

Hi,

I am trying to write a cover group which can be instantiated per master basis.

Now, this masters can access particular slaves based on the configuration.
I need to write cross coverage of the bins with accessible slaves.

So, I need to ignore slaves which are not accessible for the particular master.

All information is available during compile time.

I am not sure how can I achieve my objective here.

Any help is appreciated.

My sudo code looks like below:

module
 
class ma_cov extends uvm_component;
// UVM things
covergroup cg();
 
    m_slave: coverpoint slave_list_enum {
        bins slvs_b[] = { [ slave_list_enum.first():slave_list_enum.last() ]  };
 
        //******** NEED HELP HERE ****************
        //Need to write ignore bins here for the slaves which are not accessible for current master
        //****************************************
 
    }
endgroup
 
function new (string name, uvm_component parent);
cg = new();
cg.set_inst_name(name); // sets the inst name as current master
endfunction
 
endclass
 
ma_cov m_cov[string];
string inst_name;
 
initial begin
foreach (master_list_enum[i]) begin
inst_name = master_enum_list[i]
m_cov[master_list_enum[i]] = new (inst_name, null);
end
end
 
endmodule

Thanks,
Chintan

Answer 1

Solution

dave_59

Forum Moderator

10658 posts

November 14, 2016 at 9:03 pm

In reply to chintanm86:
You did not explain how the ma_cov class would know which slaves are to be ignored. However the covergroup feature you want is a bin set expression. You can populate an array with the slaves that are accessible and use the array when declaring the covergroup.

covergroup cg();
    option.per_instance = 1;
    m_slave: coverpoint slave_list_enum {
        bins slvs_b[] = { master_slave_list };
    }
endgroup
 
function new (string name, uvm_component parent);
   master_slave_list = // needs to be set before cg construction.
   cg = new();
   cg.set_inst_name(name); // sets the inst name as current master
endfunction
endclass

— Dave Rich, Verification Architect, Siemens EDA

Answer 2

chintanm86

Forum Access

23 posts

November 14, 2016 at 9:32 pm

In reply to dave_59:

Hi Dave,

Thanks for the answer.

In my env, I have an associative array which contains the master and slave list for that master.
So, its possible to populate another list of slaves which needs to be ignored.

But, if your solution can generate the bins only for the accessible slaves than I dont need ignore_bins anymore.

Just one question:
m_slave: coverpoint slave_list_enum {
bins slvs_b[] = { master_slave_list };

Here,
slave_list_enum is the enum type variable which contains all the slaves.
and master_slave_list is the list containing the slaves which are accessible by current master.

Do I need to declare this master_slave_list as same enum type in this class?

This will generate bins only for list I pass, right?

Thanks,
Chintan

Languages & Standards

Methodologies

Techniques & Tools

Universal Verification Methodology (UVM)

Featured Courses

Additional Courses

Formal-Based Techniques

Analog/Mixed Signal

UVM Forum

SystemVerilog Forum

Coverage Forum

Additional Forums

Implementation Patterns

Specification Patterns

Pattern Resources

UVM Cookbook

Coding Guidelines & Deployment

Coverage Cookbook

Featured & On-Demand

On-Demand Library

Recording Archive

Conferences & WRG

Siemens EDA Learning Center

Blog & News

Verification Horizons Publication

About Us

Training

Solution

Portfolio

Explore

Siemens

Contact