I want some timing control inside a testbench function in SV. At the end of certain timing control statements,
I want to read data from an address of dut memory and return it. Something like this:
function int rdata (int addr);
//force some signals
@(posedge clk) ;
// timing control
rdata = dut_data ;
endfunction
However ModelSim throws error on using illegal timing control inside function.
I have used functions like this in Verilog before, but it seems like this is a strict rule in SV.
Is there any work-around for this requirement? Preferably without classes and all....
