Function with timing control

SystemVerilog
1

I want some timing control inside a testbench function in SV. At the end of certain timing control statements,
I want to read data from an address of dut memory and return it. Something like this:


function int rdata (int addr);
   //force some signals
   @(posedge clk) ;
   // timing control
   rdata = dut_data ;
endfunction

However ModelSim throws error on using illegal timing control inside function.
I have used functions like this in Verilog before, but it seems like this is a strict rule in SV.
Is there any work-around for this requirement? Preferably without classes and all…

2

In reply to Mitu Raj:

SV functions cannot consume simulation time. Try the same with “task”.

3

In reply to Mitu Raj:

Verilog functions can never consume time and must return their value immediately. SystemVerilog does not change that.

You can have non-blocking assignments inside a function, but the RHS get evaluated immediately, and the LHS target cannot be argument to the function or its return value.

It would help to see how you were expecting to use a function, and perhaps it is better to use a task.

4

In reply to dave_59:

If I use task I can’t use statements like “data_read <= rdata (addr);” in my initial block because task cannot return a value. I should be using something like “rdata (addr, data_read);”
Is this the only work-around?

5

In reply to Mitu Raj:

If you need the output to go through a non-blocking assignment, then you would have to do

initial begin
    ...
    rdata (addr, temp);
    data_read <= temp;
    ...

But if you are always going to make an assignment to data_read (and no other variable), then it makes more sense to put the NBA in the function or task.

task rdata (int addr);
   //force some signals
   @(posedge clk) ;
   // timing control
   data_read = dut_data ;
endtask