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  • Function Coverage: default bins

Function Coverage: default bins

SystemVerilog 6464
Default bin 1 illegal bins 4
prashant.kaushik
prashant.kaushik
Full Access
38 posts
April 19, 2016 at 2:48 am

Per 1800-1200 SV LRM, page 525 "The default is useful for catching unplanned or invalid values".

It seems me that as a user whether values for default bins is generated or not, it can be know only after looking coverage report.

Is there any alternate to know about it, i.e could a Error or Warring be reported in log?

[I am aware of that when value defined as illegal bins is sampled it reports a run time error. Thing is that for illegal bins, need to explicit define value, while for default bins tool make list of value which are not defined in coverpoint. I see advantage of default over illegal when there are large set of values which should not be generated.]

pkaushik

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dave_59
dave_59
Forum Moderator
10909 posts
April 19, 2016 at 8:10 am

In reply to prashant.kaushik:

The default bins and illegal bins are meant as debugging aids for the person developing the coverage model. They should not be used as a model checker. You have no control over how the messages get reported or suppressed that you would have with an assertion or a simple if-statement with a uvm_error message.

That being said, you could use bin expressions to make it easier to express your bin set values.

module top;
 
   bit [2:0] a,b[],c[];
 
   covergroup cg;
      coverpoint a {
	 bins          mode1 = {3'b001};
	 bins          mode2 = {3'b010};
	 illegal_bins  no_b  = b;
	 illegal_bins  not_c   = a  with (!(item inside {c}));
      }
   endgroup : cg
   cg cg_h;
 
   initial begin
      b = {3,4};
      c = {1,2,3,4,5,6};
      cg_h = new;
      repeat(8) begin
      	 cg_h.sample();
	 a++;
      end
   end
endmodule : top

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