Four states random input generator

How can I randomize say 1-bit two inputs (in0, in1) such that each has uniform distribution of input values; say input = 0 30%, input =1 30%, input = x 20% and input = z 20%?

In reply to emad hamadeh:


import uvm_pkg::*; `include "uvm_macros.svh" 
// How can I randomize say 1-bit two inputs (in0, in1) 
// such that each has uniform distribution of input values; 
// say input = 0 30%, input =1 30%, input = x 20% and input = z 20%?
module top; 
	logic in0, in1;
	logic [1:0] a, b;
	initial begin : init1
		repeat(10) begin : rpt1 
			if (!randomize(a, b)  with 
					{ a dist {2'b00:=3, 2'b01:=3, 2'b10 :=2, 2'b11 :=2 };
					  b dist {2'b00:=3, 2'b01:=3, 2'b10 :=2, 2'b11 :=2 };
					}) `uvm_error("MYERR", "This is a randomize error")
			case (a)
			  2'b00 : in0=1'b0;
			  2'b01 : in0=1'b1;
			  2'b10 : in0=1'bX;
			  2'b11 : in0=1'bZ;
		    endcase  
		    case (b)
		    2'b00 : in1=1'b0;
		    2'b01 : in1=1'b1;
		    2'b10 : in1=1'bX;
		    2'b11 : in1=1'bZ;
		    endcase  	
		    $display("a=%d, b=%d, in0=%b, in1=%b", a, b, in0, in1); 
		end : rpt1
	end : init1
endmodule  
// simulation results
a=1, b=2, in0=1, in1=x
# a=1, b=3, in0=1, in1=z
# a=3, b=0, in0=z, in1=0
# a=3, b=1, in0=z, in1=1
# a=2, b=0, in0=x, in1=0
# a=2, b=1, in0=x, in1=1
# a=0, b=0, in0=0, in1=0
# a=2, b=1, in0=x, in1=1
# a=1, b=0, in0=1, in1=0
# a=0, b=2, in0=0, in1=x	 
 

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us


In reply to emad hamadeh:

If it’s a uniform distribution then the probability for each value would be 0.25. What you’re asking for is a weighted distribution.

In reply to ben@SystemVerilog.us:

thanks a lot Ben…I had to change this a bit to make it as a two dimensional array.

In reply to sbellock:

you are right…thanks