Forever loop and fork...join_any

SystemVerilog
1

Hi,
I am trying to write a SV checker to check for req ack protocol.
after seeing a req, i should see ack within 4 cycles.

To do this, i am using forever loops inside fork…join_any.


module req_ack;
  
  bit req,ack,clk;
  //logic clk;
  int count;
  
  always @ (posedge req) begin
    
    fork 
      begin : label_1
        $display("thread0");
        forever @ (posedge clk) 
          begin 
          $display("saw clk");
          count = count + 1;
          $display("clk count is %0d", count);
          if (count == 4) begin
            $display("timeout for ack");
            //disable label_2;
          end          
        end        
      end
      
      begin : label_2        
        forever  @ (posedge ack) 
          begin           
          $display("received ack");
           //disable label_1 ;          
        end        
      end      
    join_any
    
  disable fork;                  
       
      
  end  
      
      
  initial begin
     
     #10;

      req = 1;
     
     #60;
     
      ack = 1;
     
   end
   
   
   initial begin 
     
     # 100;
     
     $finish;
     
   end
   
    initial clk = 0;
    always #5 clk = ~clk;  
        
      
      
 endmodule

I see that this does not give expected results.
After hitting timeout, the disable fork does not kill the forever loops.

I tried using disable label which works fine but it is not a recommended approach.

2

Any reason why you would not use a simple assertion for this requirement?



sequence  req_ack_seq; 
  @(posedge  clk);
         req ##[1:4] ack;  
endsequence

property req_ack_prop; 
    reg_ack_seq; 
endproperty 

assert property (req_ack_prop);
3

In reply to logie:

Agreed about using an assertion for checking this protocol.

The reason your code is not working is because both forever loops never end and you can never get past the join_any. You can add a break statement in the first forever loop which ends that loop so you can get to the disable fork statement.

4

In reply to dave_59:


// Forassertions you need an implicationoperator 
ap: assert property(@ (posedge clk)  @(posedge  clk);
         $rose(req) |->  ##[1:4] ack);

On the use of fork-join see my paper

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact http://cvcblr.com/home.html
** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
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5

In reply to dave_59:

Thanks Dave.
I was just looking for alternatives for SVA.

When reqs are pipelined, SVA might give false pass.
I will try adding the break statement.

6

In reply to ben@SystemVerilog.us:

Thanks Ben.