Forcing on a port

SystemVerilog
1

Hi,

Hi have a small piece of code something like below.

The hierarchy is top.u_t1.u_t2.u_t3.u_t4

Each module has 2 input ports which are connected to 2 ports of the internal module.

I want to force value of 1 to the port u_t1.u_t2.u_t3.u_t4.i2 after some time without affecting i2 input of all other modules.

Please let me know how to do it without changing code for module t1, t2, t3 and t4.

module top();
  logic a, b;
  initial
  begin
    $display("Hi");
    a=0;
    b=0;
    #10 a = 1;
    #20;
    force top.u_t1.u_t2.u_t3.u_t4.i2 = 1;
    #20;
    $display("Done");
  end

t1 u_t1(.i1(a), .i2(b));

  module t1(input i1, i2);
    t2 u_t2(.i1(i1), .i2(i2));
  endmodule : t1

  module t2(input i1, i2);
    t3 u_t3(.i1(i1), .i2(i2));
  endmodule : t2

  module t3(input i1, i2);
    t4 u_t4(.i1(i1), .i2(i2));
  endmodule : t3

  module t4(input i1, i2);
  endmodule : t4

endmodule : top
2

The force cannot be done as you wish because the i2 input is declared as a wire, and you cannot force only part of a wire. In Verilog, the wires of the upper and lower modules become one because of port collapsing, and port directionality is not enforced.

If the port had instead been declared as input var logic i2, then the port connection becomes a continuous assignment that flows uni-directionally. A force at the lower level would not flow up to the higher levels.