Force statement in System Verilog under if begin end

SystemVerilog
1

Hi,

Is there a way force statement can execute before its preceding statements in System Verilog within a begin end?

I have below code were my force is getting executed before configuring a some register in statement 2.

if(condition) begin

register write 1..;
register write 2..;

force abc.dut.signal_a = 1'bx;
force abc.dut.signal_b = 1'bx;
force abc.dut.signal_c = 1'bx;

end

Results: Force 1’bx for signal_a,b and c is appearing ~80 ns before the register write 2 being executed? Am I missing something here?

2

In reply to abhi9891:

it might be the case where Register write can take some time to reflect the value at destination.
The response for that write can come before.

3

In reply to abhi9891:

The possible reason could be,

  1. write protocol may not have response phase
  2. if it has a response phase, your driver logic is not waiting till the response phase to complete

Possible solution,

  1. Use backdoor method for Register access, which takes 0 simulation time
  2. Wait for response phase to complete