Force any random array location by passing the array index

SystemVerilog
,
1

Hi,

I am trying to force any random location of an array in each run. I tried below code but its not working.

std::randomize(n) with {n inside{[794:845]};};
force bmd_tb.bmd.alpha.DATA_ARRAY[n]={37{1’b1}};

Below code (with uvm_hdl_force) for the same is working but simulation time is too much.
std::randomize(n) with {n inside{[794:845]};};
uvm_hdl_force($sformatf(“bmd_tb.bmd.alpha.DATA_ARRAY[%0d]”,n),{37{1’b1}});

can you please provide input to achieve this by force instead of using uvm_hdl_force.

Thanks

2

In reply to amit2229:

The SystemVerilog force statement requires the LHS to have constant selects. You might be able to work around this issue by writing:

case(n)
 794: force bmd_tb.bmd.alpha.DATA_ARRAY[794]={37{1'b1}};
 795: force bmd_tb.bmd.alpha.DATA_ARRAY[795]={37{1'b1}};
 ...
 845: force bmd_tb.bmd.alpha.DATA_ARRAY[845]={37{1'b1}};
endcase

The performance issue might be related to forcing particular elements of an array, or the way you turned of optimizations to allow access to to the array by string names. You should contact your tool vendor to investigate.