Flag assertion still running at end of simulation as an error

SystemVerilog
1

Is there a way to flag an assertion that is still running at the end of the simulation as an error?

This is specifically for Questa, at least one other vendor has a switch for it.

Thanks,

Scott

2

In reply to snixon:

It depends on what you mean by “still running”. SystemVerilog assertions have strong properties like s_until that must be satisfied at some future clock cycle, otherwise it is considered a failure.

3

In reply to dave_59:

By still running I mean still active, i.e. it triggered the start but the implication was not met when the simulation ended.

4

In reply to snixon:

You can still code this strongly so that an assertion must pass during a simulation, otherwise it is a failure.

If you’re still looking for a magic switch, you 'll have to look at your tool’s User Manual for dealing with active assertions at the end of simulation.

5

In reply to dave_59:

Would prefer to code it, as some other assertions may still be running yet not represent failures.

Is the “until” properties the recommended way of coding it?

6

In reply to snixon:

See SVA : Property is a tautology | Verification Academy

7

In reply to dave_59:

That looked promising, but adding the “strong” keyword to my implication did not lead the the still running assertion being flagged at the end of the simulation?

8

In reply to snixon:

This was flagged as an assertion error after executing $finish:

module top;
   bit clk,req,gnt;
   property p;
      @(posedge clk) req |-> strong(##[0:$] gnt);
   endproperty
   assert property (p);
   always #1 clk = ! clk;
   initial begin
      @(negedge clk)
      @(negedge clk) req  = 1;
      @(negedge clk) req  = 0;
     @(negedge clk) //gnt = 1;
      @(negedge clk)
      $finish;
   end
endmodule
9

In reply to dave_59:

Unfortunately not in my simulator version (Questa 10.6c_3).

No error, after $finish assertion is still shown as active.

Would have been a really elegant solution too…

10

In reply to snixon:

# //  Questa Sim-64
# //  Version 10.6c_3 linux_x86_64 Dec 21 2017
# //
# //  Copyright 1991-2017 Mentor Graphics Corporation
# //  All Rights Reserved.
# //
# //  QuestaSim and its associated documentation contain trade
# //  secrets and commercial or financial information that are the property of
# //  Mentor Graphics Corporation and are privileged, confidential,
# //  and exempt from disclosure under the Freedom of Information Act,
# //  5 U.S.C. Section 552. Furthermore, this information
# //  is prohibited from disclosure under the Trade Secrets Act,
# //  18 U.S.C. Section 1905.
# //
# Loading sv_std.std
# Loading work.top(fast)
# run -all
# ** Note: $finish    : strong.sv(14)
#    Time: 10 ns  Iteration: 1  Instance: /top
# ** Error: Assertion error.
#    Time: 10 ns Started: 5 ns  Scope: top File: strong.sv Line: 6
# End time: 23:09:48 on Oct 23,2019, Elapsed time: 0:00:11
# Errors: 1, Warnings: 0

Same result in two other vendors’ simulator.
EDAPlayground

11

In reply to dave_59:

Doh, when you run with the “-onfinish stop” option enabled while doing interactive debug the simulation never actually ends hence no error message. Actually terminating the simulator leads to the expected error.

Thanks for your persistence, I will update my assertions to use the strong keyword!

Scott