AP_DATA_FIRST_BIT: assert property(@(dclk_p) (p_data_first_bit(d1_p || d2_p || d3_p || d4_p)))
else uvm_pkg::uvm_report_error(“AP_DATA_FIRST_BIT”,“First bit of data sample is not on rising edge of the clock”);
Error: Instead of checking only the first match, Assertion checks whole data sequence and emits an error.
Anything wrong in the sequence written?
I have implemented an Assertion which checks “if the first bit of the data sample is at the rising edge of the clock”
//AP_LVDS_DATA_FIRST_BIT
sequence s_data_sequence(data);
(##[0:$] (data), $display($time,“FIRST MATCH DATA”) );
endsequence
property p_data_first_bit(logic data);
disable iff (!reset)
first_match(s_data_sequence(d1_p || d2_p || d3_p || d4_p)) |-> $rose(dclk_p);
endproperty
AP_DATA_FIRST_BIT: assert property(@(dclk_p) (p_data_first_bit(d1_p || d2_p || d3_p || d4_p)))
else uvm_pkg::uvm_report_error(“AP_DATA_FIRST_BIT”,“First bit of data sample is not on rising edge of the clock”); Error: Instead of checking only the first match, Assertion checks whole data sequence and emits an error.
Anything wrong in the sequence written?
I don’t believe that you are using the $rose correctly. Specifically, $rose returns true when the sampled value of a Boolean signal argument transition is true at the current cycle (i.e., least significant bit of the expression==1’b1) and FALSE in the previous cycle (i.e., was 0, X, or Z), with respect to the clock of its context, otherwise it returns FALSE.
Thus, for
ap_rose: assert property(@(clk) 1|-> $rose(clk));
@ the rising edge of clk the sampled value of **rose(clk)** is 0 since the sampled value of clk in the PREPONED region is 0 and the previous sampled value of clk ==1.
2. **first_match**(##[0:](expression) |-> some_sequence
This is really the SAME thing as
(expression) |-> some_sequence
This is because at every event, if the expression==0, the assertion is vacuous. All that the first_match() does is just add more overhead on the simulator.
3. This is what I think you need.
Hi Ben,
Thanks for your Feedback. It truly helps!!
But, the Assertion msut stop after it finds first bit of data on the rising edge. But it keeps on checking and asserts an error when condition is not met.
In reply to bhataksh:
It sounds like your assertion is NOT expressing your requirements.
You say that the assertion must stop after it finds first bit of data on the rising edge. But the following assertion states the following:
// At every clock edge of dclk_p, if either of the following bits ==1, then dclk_p==0.
// Those bits include d1_p, d2_p, d3_p, d4_p
//An assertion of this property is tested at every clock edge of dclk_p,
// and last ONLY ONE cycle.
property p_data_first_bit(logic data);
@(dclk_p) disable iff (!reset)
(d1_p || d2_p || d3_p || d4_p) |-> dclk_p==0);
endproperty
When you say assertion must stop after it finds first bit of data on the rising edge
Exactly, what do you mean by that? Anyone of those bits at any cycle ==1, then you have a rising edge? That’s what you have expressed.
you seem to imply a sequence that lasts more than ONE cycle.
I suggest that you express your requirements in English. If the following are your requirements:
There is a sequence of bits that are active over several cycles.
These bits are checked at the clock edges of dclk_p
If d1_p is followed some n cycles later by d2_p, and then some n cycles later by d3_p, some n cycles later by d4_p, then that last d4_b mys occur at the rising edge of that clock.
Notice that we are now talking about a sequence that lasts more than one once.
This sequence is started at every occurrence of d1_p==1
In that case, you can do something like:
property p_data_first_bit(logic data);
@(dclk_p) disable iff (!reset)
(d1_p[->1] ##1 d2_p [->1] ##1 d3_p [->1] ##1 d4_p[->1]) |-> dclk_p==0);
endproperty
// NO first_match() is needed with the goto operator
Again, state your requirements in ENGLISH first!!!
What your first wrote was about a sequence of one cycle, and at every clocking event it either matches or does not match; thus the first_match() is totally meaningless.
Ben Cohen http://www.systemverilog.us/ben@systemverilog.us
Hi Ben,
As I stated earlier, the requirement is, “**the first bit of the data sample must be at the rising edge of the clock”
**
Meaning, Assertion should ONLY check first bit of the data sample. In this case
there are 4 data lines which start transferring data when clock is enabled
The Assertion should check if and only if FIRST bit of data sample (d1 or d2 or d3 or d4) is on rising edge of the clock. If YES, Assertion must stop checking further and assert PASS, if not it should stop checking and assert an ERROR.
The Assertion ONLY meant to check first bit not the entire sequence (that is why I used first_match earlier)
If I understand you correctly what you basically want to to if stop the checking of an assertion when a certain condition occurs.
The following assertions demonstrate the concept, one where the fail is on the first PASS, the other on the first FAIL. The concept is to use in the action block the**$assertoff** on the selected assertion label.
AP_DATA_FIRST_BIT_PASS: assert property(@(dclk_p) (d1_p[0] || d2_p[0] ||d3_p[0] || d4_p[0]))
$assertoff (0, AP_DATA_FIRST_BIT_PASS);
else uvm_pkg::uvm_report_error("AP_DATA_FIRST_BIT","First bit of data sample is not on rising edge of the clock");
AP_DATA_FIRST_BIT_FAIL: assert property(@(dclk_p) (d1_p[0] || d2_p[0] ||d3_p[0] || d4_p[0]))
else begin
$assertoff (0, AP_DATA_FIRST_BIT_FAIL);
uvm_pkg::uvm_report_error("AP_DATA_FIRST_BIT","First bit of data sample is not on rising edge of the clock");
end
