module shift_ex;
reg [511:0] in='h55555555;
reg [3:0] o;
reg clk;
task shift_logic();
for(int i=0;i<=128;i++)
begin
@(posedge clk)
o <= (in << 4);
end
endtask
initial begin
clk<=0;
forever begin
#5
clk<=~clk;
end
end
initial begin
$dumpfile("top.vcd");
$dumpvars;
#100;
$finish;
end
initial begin
shift_logic();
end
endmodule
in the above code “o” is my output. the output is not as expected. i have tried in other way its working. i am attaching the link for reference - shifter example - EDA Playground