Final_block

SystemVerilog
, , , ,
1

why the monitor is not showing in final_block, but shown in initial_block.

// Code your testbench here
// or browse Examples
module tb_top;
   bit [3:0] counter;
   bit [3:0] pass;
   bit [3:0] fail;
 
   initial begin
      for (counter = 0; counter < 13; counter ++) begin
         #1;
         if (counter % 2) 
            pass++;
         else 
            fail++;
      end
   end
 
   final begin
      $display ("----------------------------------------");
      $display ("          REPORT @ %0t ns            ", $time);
      $display ("----------------------------------------");
      $monitor ("       Pass  : %0d", pass);
      $display ("       Fail  : %0d", fail);
   end
endmodule
2

In reply to dorababu:

Initial block starts getting executed during simulation time t=0 while the Final block gets executed when the simulation is completed.
$monitor displays the values of its parameters EVERY time ANY of its parameter changes value.
so when simulation is finished it will not show any value under $monitor statement as no change in the value.
$display will show the final value of the variable.