Fibonacci series printing all zeros

SystemVerilog
1

Hi. I have written code here.I want that first argument tells length of series and second argument is series itself, but in this code it always gives all zeros. what can be the issue?

2

In reply to juhi_p:

variables not initialized properly here

code:
// Code your testbench here
// or browse Examples
module abc;
bit [10:0] a;
int f_b [$];

task automatic fb (input bit[10:0] b,inout int fib[$]);
fib[0] = 0; fib[1] = 1;
for (int i = 2; i < b; i++) begin
fib[i] = fib[i -1 ] + fib[i-2];
end
endtask

initial begin
a=10;
fb(a,f_b);
$display(“%p”,f_b);
end
endmodule

3

In reply to juhi_p:

Hi,

see this line : fib[b] = fib[b-1] + fib[b-2];

You have passed b as 3, so fib[3] = fib[2] + fib[1];

But fib[2] and fib[1] array entries are zero so you are ending up with all zeroes.

You need to fix your factorial series logic.

4

Thanks, for you’re input. I wanted to have recursive function so, I have changed some logic and now it’s working fine.