$fell not working

SystemVerilog
1

I have a condition like the one below:

@(posedge clk) 
 a && $fell(b) |-> ##1 $fell(c)......

I see that $fell(c) is failing even when there was a transition from 1 to 0. Any specific reason for it?

2

In reply to abhi9891:

once try this
property p1;
@(posedge clk)
a && $fell(b) |=> $fell(c)
endproperty

assert property(p1);

3

In reply to vickyvinay:

Still the same issue.

4

In reply to abhi9891:

Transition of signal c, from 1->0 should be before @(posedge clk).
So that in PrePone region correct value gets sampled for $fell(c) detection.