always@(posedge clk)begin
p1: assert property(
disable iff(rst_n!==1)
$fell(a) |-> ##[1:$] (b==1'b0) ##[1:$] (c==1'b0))
else
begin
//error code
end
end
What i observe in simulation, that when rst_n goes 1, during that time assertion is failing even though ‘signal a’ is not changing during several cycle before and after of rst_n =1.
In reply to vineet_sharma:
I do not see what you are experiencing. Modify this code and demonstrate your case.
// Edit code - EDA Playground
// missed the $sampled(b)