$fell issue in sva

Hi,

I have written an sva.

code snippet:

always@(posedge clk)begin
p1: assert property(
disable iff(rst_n!==1)
$fell(a) |-> ##[1:$] (b==1'b0) ##[1:$] (c==1'b0))
else

begin
//error code
end
end

What i observe in simulation, that when rst_n goes 1, during that time assertion is failing even though ‘signal a’ is not changing during several cycle before and after of rst_n =1.

In reply to vineet_sharma:
I do not see what you are experiencing. Modify this code and demonstrate your case.
// Edit code - EDA Playground
// missed the $sampled(b)


import uvm_pkg::*; `include "uvm_macros.svh" 
module top; 
    bit clk, a, b, c, rst_n;  
    default clocking @(posedge clk); endclocking
    initial forever #10 clk=!clk;   
     
    always@(posedge clk)begin
        p1: assert property(
        disable iff(rst_n==0)
        $fell(a) |-> ##[1:$] (b==1'b0) ##[1:$] (c==1'b0))
          else $display("%t rst_n= %b, %b", $realtime, rst_n, $sampled(b));
    end


 initial begin 
   $dumpfile("dump.vcd");
   $dumpvars(rst_n, a);
    //$monitor("%t 0x%x, 0x%x", $time, rst, a);
    
   repeat(4) @(posedge clk);
   rst_n <= 1'b1;
   a <= 1'b1; 
   repeat(4) @(posedge clk);
   $stop; 
   end  
endmodule  

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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