$fell assertion failing at first clock edge

SystemVerilog
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1

I am trying to check a basic handshake protocol with the $fell and $past tasks.

@(posedge clk) disable iff (!resetn) $fell(valid) |-> $past(enable)

However at the first clock edge in the testbench, the assertion is triggering. A bit of searching shows similar issues from others but no real solution.

At the first positive clock edge resetn is high and valid is low and enable is high. I am not sure why this causes the assertion to trigger or how to deal with this in the assertion itself (assume I cannot play with the testbench and reset mechanisms).

2

In reply to cwcar:

In the first clock $past(var) is the value of var at initialization; there is no history on var yet.
The simple fix is to give $past a past
@(posedge clk) disable iff (!resetn) ##1 $fell(valid) |-> $past(enable)

1800; If there do not exist k strictly prior time steps in which the event ev iff expression2 occurred, then the value returned from the $past function is the default sampled value of expression1 (see 16.5.1 ).