Extracting type of variable within a macro

SystemVerilog
, ,
1

I am writing a macro to be used by others, and I would like it to require as little input as possible. As such, I would like to be able to pass in a variable as an argument, extract the type, use the type to declare a new variable, and do some other things.

So the idea is something like this:

`define DO_STUFF(var) \
$typename(var) var``_new; \

However this doesn’t work. It seems the “$typename(var)” is not compiled when the macro is expanded, since I get the syntax error “(expanding macro): token is ‘$typename’” when I try to run this.

However this runs fine:

`define PRINT_TYPE(var) \
  initial begin \
    $display("Got type: %s", $typename(var)); \
  end \

Is there any way to do this? It doesn’t necessarily need to use $typename, but any way to get the type of a variable without explicitly passing it in would be great.

2

In reply to jms8:

$typename returns a string, and you can’t use a string to declare a new variable.

You want to use the builtin type() operator.

`define DO_STUFF(var) \
type(var) var``_new; \
3

In reply to dave_59:

Thanks for your answer, but it looks like it doesn’t compile with my simulator.

I have:


`define DO_STUFF(var) \
type(var) var``_new; \

module top();

  logic a;

  `DO_STUFF(a)

endmodule

and I compile with:

vcs -sverilog -R experiment.sv

Then I get the error:

Parsing design file 'experiment.sv'

Error-[SE] Syntax error
  Following verilog source has syntax error :
  "experiment.sv", 9 (expanding macro): token is 'type'
    `DO_STUFF(a)
                ^
  System verilog  keyword 'type' is not expected to be used in this context.

#0, DO_STUFF(var=a) : "experiment.sv":3
full expansion of macro (DO_STUFF), error at line 1
=>type(a) a_new; 
  
1 error
CPU time: .052 seconds to compile

Any other ideas?

4

In reply to jms8:
Try changing your macro to

`define DO_STUFF(arg) \
var type(arg) arg``_new; \

See the 1800-2012 LRM section 6.23 Type operator.

5

In reply to dave_59:

Thanks for pointing me to the correct section of the LRM, and for correcting my syntax issues.
Unfortunately my simulator still doesn’t seem to be able to handle the type operator. I have tried both of these pieces of code:

`define DO_STUFF(arg) \
var type(arg) arg``_new; \

module top();

  logic a;

  `DO_STUFF(a)

endmodule

module exp_2();

  int tp1,tp2;
 
  initial begin
 
    var type(tp1) tp3;
 
  end

endmodule

(From this related question: Help on Type operator section in LRM | Verification Academy)

Both give me the compile error:

Parsing design file 'experiment2.sv'

Error-[NYI] Not Yet Implemented
experiment2.sv, 7
  Feature is not yet supported: Type operator not supported                 

        "experiment2.sv", 7: token is '('
    var type(tp1) tp3;
             ^
1 error

Is it possible my version of vcs doesn’t have ‘type()’ for some reason? In the forum question I point to above, it seems that the poster’s simulator also cannot handle the type operator. I have a fairly recent version of vcs, so it seems surprising that type() is not there. I will ask my coworkers if they have any idea. Maybe our simulator is different in some way.

Thank you so much for help and patience with this. I really appreciate it.