Extend value to vector size in SV

SystemVerilog
,
1

A little help with the syntax please:

I have a vector of a parameterizable size and I want to assign a value that extends to the size of the vector. The line I want to change is this one: vector <= 20; in the following code:


parameter int c_vector_bw = 5;
var logic [c_vector_bw-1:0] vector;

always_ff @(posedge clk) begin: p_vector
    if (vector_ld)
        vector <=  20;
    else
        vector <= '{default:'0};
    end
end: p_vector

I would like to write something like:

vector <= $size(20,c_vector_bw);

but the previous doesn’t do what I want.

The idea is to do something like the VHDL function:


function RESIZE (ARG: SIGNED; NEW_SIZE: NATURAL) return SIGNED;
vector <= $resize(20,c_vector_bw);

How do I do that in SystemVerilog?

Thank you for the help you can provide!

2

In reply to stefaniecg:

First of all, there is no need to do this in Verilog/SystemVerilog - all vectors are implicitly extended or truncated to fit into the needed context.

But SystemVerilog has a cast operator that can be used to explicitly show your intent, or to change the context if it does not match what you want.

You can do

 P'(expression).      // changes the width of the expression to match the constant P
                        // - signedness remains the same 
 signed'(expression)  // changes the signedness of an expression
 unsigned'(expression) // -  width remains the same
 typename'(expression) // changes the width and signedness to match a user defined typename
                         // can also be used to reshape arrays and structs.
3

In reply to dave_59:

Thank you for drooping some knowledge!