hi
i have this code, which is a part of a big FSM that i use switch-case for the states:
if (lane_work_present) begin //means lane[curr_lane_for_calc] started work at last clock, so we need to change its en from 1 to 0
lane_en[curr_lane_for_calc] <= 0;
lane_work_next <= 0;
end
for the line lane_en[curr_lane_for_calc] <= 0; i get the error in the topic
the declaration for those variables are:
parameter LANES_SIZE = 3;
logic lane_work_present;
logic curr_lane_for_calc[LANES_SIZE-1:0];
logic lane_en[LANES_SIZE-1:0];
the code should be synthesable
as far as i understand, there is a problem with the indexing of the lane_en array, but i don’t understand what should i do to index it in the right way
would appreciate your help
thanks
Shahar