Expanding Macros

SystemVerilog
1

Hi,

I have a parameter that i pass in from the top level module. I need to use that parameter as a define and use that define inside the assign statement. how do i do it?



`define TEST <hier>.tb1

module tb#(string hier="")(input logic clk);

assign <hier>.clk   = clk;
  
endmodule

module hi;
  logic clk;
  tb#(.hier("hello")) tb1(.clk(clk));
endmodule
2

In reply to rag123:

You cannot use strings as identifiers. And your example does not show how you want the TEST macro to be expanded. How does “hello” play into all of this?

3

In reply to dave_59:

The string is used in defining the macro and the macro is used in assigning the signal.

4

In reply to rag123:

I do not understand what it is you are trying to do.