Exact use case of SystemVerilog virtual functions

SystemVerilog
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1

Hi,

I have been able to grasp to an extent the concept of virtual functions in SystemVerilog. It says “If a function is defined virtual, then the run-time decides the function to be called based on the object type referred / pointed to”. But what is the exact use-case or scenario where it will be required in verification? Please do provide me some practical examples that we encounter in our day-to-day work.

Thanks.

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This is a very basic principle of object oriented programming and there are many online resources available to help you. Try https://verificationacademy.com/courses/introduction-to-the-uvm, specifically the section on object oriented programming.

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In reply to dave_59:

Hello Dave,

Thanks for your help.