Hi
I have the following piece of code:
`timescale 1ns/1ps
module tb2;
reg clk = 0;
reg a=0;
reg b=0;
reg c=0;
initial forever #5 clk = ~clk;
always @ (posedge clk) begin
$display("updating a");
a <= ~a;
end
always @(*) begin
$display("updating c");
c = b;
$display("updating b");
b = a;
end
endmoduleAfter I simulate this, I get the following output wave:
Here is the transcript output:
Quote:
# updating a
# updating c
# updating b
# updating a
# updating c
# updating b
...
Apparently, each time 'a' is inverted, the always block is evaluated once, which entails assigning the old value of 'b' to 'c', and then then the new value of 'a' to 'b'. What makes me wonder is that, after 'b' is updated with the new value of 'a', shouldn't the always block be evaluated one more time, causing the new value of 'b' to be assigned to 'c'? I guess this would happen if the assignments were non-blocking. Why isn't it the same with blocking assignments?
