Evaluating a Constraint expression

SystemVerilog
,
1

I have a question related to “Verilog Basics for SystemVerilog Constrained Random Verification”

Evaluating an expression consists of

— Context
— Precedence
— Casting

I have following constraint


   rand bit signed [2:0] a , b , c , d ; 
 
   rand bit signed [3:0] sum ; 

   constraint SIGN_ADDITION { 
                                sum == ( c < d ) + a + b  ; // [Q2] :: How is the Expression Evaluated ??
 			    }

My Question is :: In what order is the expression evaluated ??

I know for certain that the following steps Occur ( Not Necessarily in the order mentioned below ) ::

(a) All Operands are Size Cast to 4 bits since the max size Operand is 4-bit

(b) c < d would be evaluated first due to the parenthesis

 **( Would c < d be evaluated OR solved before Size Cast ?? )**

I believe precedence and Casting is covered here , is context covered too ??

2

In reply to TC_2017:

I think you are confusing expression evaluation order with solver ordering. It might help to think about the exhaustive 65536 (216) possible value combinations for all these random variables, the solver and evaluates the constraint expression for each combination and builds a list of the 4096 possible combinations that satisfy the constraint expression. Each time you call randomize(), one of the 4096 possible solutions gets picked with equal probability.

The point of my presentation is that expressions gets evaluated the same regardless of being inside a constraint or not. The variables a and b get extended to the size of sum, but c and d do not get extended because they are both the same size and not in the context of any other expression. (c < d) gets evaluated first because of the parentheses and because addition associates left to right.

3

In reply to dave_59:

Hi Dave ,

Result of Relational Operator is either 1’b0 OR 1’b1 the expression reduces to ::


constraint SIGN_ADDITION { 
                             sum == ( 1'b0 || 1'b1 ) + a + b  ; 
 	                  }

Due to 1’b0 OR 1’b1 the expression now is treated as Unsigned Expression .

Hence c N d would be Zero-Extended ( instead of Sign-Extended !! )

My question is while deciding the solution space for sum ,
when does the Solver decide to Zero-Extend c N d instead of Sign-Extension ?

Would be first obtain result of ( c < d ) to 1’b0 / 1’b1 and then 0-Extend it ?

4

In reply to ABD_91:

The decision on how to evaluate a constraint expression are made before the solver gets involved. You can think of all the expressions being reduced (or synthesized) into one giant Boolean expression with a single bit result, true or false.