Error while part-select in concatenation operator

SystemVerilog
1 
module bit_stuffer(data,clk,stuffed_data
    );
   input [15:0]data;
   output reg [15:0]stuffed_data;
   reg [3:0]count=0;
   reg [15:0]temp;
   input clk;
   integer i;

always@(*)
	begin
        for(i=0; i<16; i=i+1) begin
          if(data[i]==1)
             begin
             count=count+1;
             end
          else
	    count=0;
         if(count==7)
	   begin
	     stuffed_data[15:0]={data[14:i],1'b0,data[i-1:0]};
	     count=0;
	   end
      end
  end
endmodule

Error: (i)i is not a constant and (ii)Range must be bounded by constant expression

2

In reply to abhay_sonker:
Please use code tags making your code easier to read. I have added them for you.

SystemVerilog does not allow operands with variable widths in any expression. You can create a mask.

begin
  bit [1:0] mask;
  mask = (2<<i)-1;
  stuffed_data = (data&~mask)<<1 | data&mask;
  count=0;
end
3

In reply to abhay_sonker:

module bit_stuffer(data,clk,stuffed_data
);
input [15:0]data;
output reg [15:0]stuffed_data;
reg [3:0]count=0;
reg [15:0]temp;
input clk;
integer i;
always@(*)
begin
for(i=0; i<16; i=i+1) begin
if(data[i]==1)
begin
count=count+1;
end
else
count=0;
if(count==7)
begin
stuffed_data[15:0]={data[14:i],1'b0,data[i-1:0]};
count=0;
end
end
end
endmodule

Error: (i)i is not a constant and (ii)Range must be bounded by constant expression

Implicit event_expression(*) recommended only for Combinational ckt’s.