Error while loading SystemC shared lib

SystemVerilog
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1

Hi,

We are using Questasim 10.5b.

Our requirement is to

  1. create a single shared library (.so) for SystemC files. These files have SC_EXPORT_MODULE for a module_A.
    Used following commands:
    vlib sc_work
    sccom -64 -DMTI_SYSTEMC -f file_list -work sc_work
    sccom -linkshared -work sc_work
    It created “sc_work/_sc/linux_x86_64_gcc-4.7.4/systemc.so”. //no errors

  2. use the shared library (.so) in other System Verilog simulations where module_A is instantiated.
    Used following commands:
    vlib work
    vlog -64 -sv -mfcu ./top_tb.sv
    vsim -64 -c top_tb -do vsim.do -sclib sc_work/_sc/linux_x86_64_gcc-4.7.4/systemc.so
    or
    vsim -64 -c top_tb -l vsim.log -do vsim.do -sclib sc_work

** Error: ./top_tb.sv(15): Module ‘Module_A’ is not defined.

Please help us in debugging this issue.

Thanks,
Ravi

2

In reply to ravi:

This forum is not for tool issues. You should contact your support team for additional assistance.

You should also read the QuestaSim User’s Manual, as you are not following the guidance provided in it.

3

Hi cgales,

Thank you.
I could not find the relevant section in QuestaSim User Guide.pdf.

As you mentioned, I will check with support team.

4

In reply to ravi:

Chapter 9 of the QuestaSim user manual covers mixed-language simulation. There is a section on instantiating SystemC modules within Verilog/SystemVerilog.

5

In reply to cgales:

Hi cgales,
I was referring to the same section. It says to use “-sclib” option to use .so file.
But, I could not find any example on how to link/use .so file in vsim command.

It works fine if I use same work library for compiling both SystemC and Verilog files.
Issue happens when i compile systemC files to sc_work and use the generated .so in another simulation with different work directory.

My intention is to generate a single .so file for SystemC exported module and share it with other teams so that they can directly use it their verilog simulations.