Error while initializing dynamic array in System Verilog

I want to return a dynamic array from a function.But I am getting error while initializing dynamic array.Can someone please help me with how to define it.I have few specific doubts

  1. If my return type is dynamic array(out_data), do I need to allocate memory space like this(pre_processing= new [temp_i.len()] )
  2. I am getting an error while declaring bit temp_i_b,do I need to do it in some other way ?
  3. To return the data (dynamic array in this case),do we need to use “return” keyword?

Any help in this context is highly appreciable

module test1();

  typedef  bit [511:0] out_data[];
  string temp_i;

function out_data pre_processing(temp_i);
  
  pre_processing= new [temp_i.len()]  ;      
         bit temp_i_b[];
         temp_i_b=new[24](temp_i_b);
        temp_i_b[temp_i_b.size()-1:0]=temp_i.atobin();
         bit d[];
         d=new[10](d);
         
         int k,d_zero;
         bit [511:0]temp_out[];
         temp_out=new [3] (temp_out);
         bit tempor[];
         tempor=new [512*3] (tempor);
         
         
      int n;
      int T=0;
       int i=0; 
        int l=temp_i.len()*8;//l=24
        k=447-l;
            
         if(k<0)
          k=512+k;
         
     
         do
         begin
          d[i]=l%2;
          l=l/2;
          i++;             
         end while(l>0);
         
         T=l+1+k+d.size();
         n=T/512;
          d_zero=n*512-T;         
          temp_i_b={temp_i_b,1'b1};
          
          tempor[]=temp_i_b << (k+d_zero);
         foreach(d[i])
          tempor[]={tempor,d[d.size()-i-1]};
 
          foreach(temp_out[i]) begin        
          while(tempor[tempor.size()-1:0]!=0) begin
          temp_out[i]=tempor[tempor.size()-1:tempor.size()-512];
          tempor[tempor.size()-1:0]=tempor[temp.size()-1:0] << 512;
          end
          end
          
          return temp_out;
          endfunction


    out_data my_q;
    initial begin
      my_q=pre_processing(temp_i="ABC");
      $display("output=%b",my_q[0]);
        end
    

endmodule

In reply to Spriyada29:

There are couple of syntactical issues over here.

  1. You can not declare the variables anywhere in between the statements. Since the variables that are declared has a scope of a particular block, they must be declared at the top.

The variable declarations must be immediately after the function definition. Refer SystemVerilog IEEE 1800-2012, section 13. All variables in a task or function must be declared before any operation. A good practice is to always declare your variables at the top of function/block.

  function out_data pre_processing(string temp_i);
  bit temp_i_b[];  // Declare all the variables first
  bit d[]; 
  int k,d_zero;
  bit tempor[];
  bit [511:0]temp_out[];
    
  int n;
  int T=0;
  int i=0; 
  int l;
  // .. other variables declaration
  pre_processing= new [temp_i.len()]  ;      
         
  temp_i_b=new[24](temp_i_b);
  temp_i_b[temp_i_b.size()-1:0]=temp_i.atobin();

As a side note, you can declare the variables at the start of begin…end block also. Refer to similar issue over here.

  1. I didn’t get the intention of these lines. They are syntactically incorrect. What is the use of “[]” over here?

  tempor[]=temp_i_b << (k+d_zero);
  foreach(d[i])
  tempor[]={tempor,d[d.size()-i-1]};

  1. While creating the object, the arguments can be passed by name or by position. The object creation line is incorrect over here. Following are the methods to pass an argument to the function.
my_q=pre_processing(.temp_i("ABC")); // by name
my_q=pre_processing("ABC"); // alternative way, by position

In reply to sharvil111:

I rectified the points mentioned by you but I have couple of more doubts.

1.In the 2nd Point I am trying to shift temp_i_b by (k+d_zero) times to the left and store it in tempor. I did updated the code as

tempor[tempor.size()-1:0]=temp_i_b << (k+d_zero)

but it’s throwing me an error The range in array slice is illegal:. CAn you help me with ?

  1. I am not able to convert my ASCII string to its binary equivalent using
atobin()

. IS there any other way,I can achieve it? The input string I give,I need to convert it into binary and do certain operation on it.

In reply to Spriyada29:
It very hard to follow what you want to do when you do not understand SystemVerilog and you are trying to code in SystemVerilog. Can you explain what operation you want to perform with using SV code? The post the latest code you have and give an example of what the input and output to the function should be.

In reply to Spriyada29:

As Dave mentioned, it is very difficult to get the intent of the code. Please post the minimum compilable code.

As far as I got, “tempor” is a dynamic array of bit type. Each entry is of single bit wide. Also, the “temp_i_b” is a single bit wide. First of all, you need to give index of “temp_i_b”. Also, shifting a single bit entry and storing it in single bit wide entry seems fuzzy to me.

tempor[tempor.size()-1:0]=temp_i_b[<some index>] << (k+d_zero)

Please post more information about the code and the updated code.