In the below code i am getting this error:
ERROR: [VRFC 10-2991] ‘a_source_ctrl’ is not declared under prefix ‘ctrl_i’
hwpe_stream_source #(
.DATA_WIDTH ( 32 ),
.DECOUPLED ( 1 )
) i_a_source (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.test_mode_i ( test_mode_i ),
.clear_i ( clear_i ),
.tcdm ( tcdm_fifo_0 ), // this syntax is necessary for Verilator as hwpe_stream_source expects an array of interfaces
.stream ( a_prefifo.source ),
.ctrl_i ( ctrl_i.a_source_ctrl ),
.flags_o ( flags_o.a_source_flags ),
.tcdm_fifo_ready_o ( a_tcdm_fifo_ready )
);
Can not figure out why i am getting this error.
dave_59
2
In reply to Rana Adeel Ahmad:
Cannot help without seeing the definition of ctrl_i where it declares a_source_ctrl.
In reply to dave_59:
typedef struct packed {
hwpe_stream_package::ctrl_sourcesink_t a_source_ctrl;
hwpe_stream_package::ctrl_sourcesink_t b_source_ctrl;
hwpe_stream_package::ctrl_sourcesink_t c_source_ctrl;
hwpe_stream_package::ctrl_sourcesink_t d_sink_ctrl;
} ctrl_streamer_t;
In reply to Rana Adeel Ahmad:
This is declared in the package.
In reply to dave_59:
Here in this module the ctrl_i is declared.
``` verilog
module mac_streamer
#(
parameter int unsigned MP = 4, // number of master ports
parameter int unsigned FD = 2 // FIFO depth
)
(
// global signals
input logic clk_i,
input logic rst_ni,
input logic test_mode_i,
// local enable & clear
input logic enable_i,
input logic clear_i,
// input a stream + handshake
hwpe_stream_intf_stream.source a_o,
// input b stream + handshake
hwpe_stream_intf_stream.source b_o,
// input c stream + handshake
hwpe_stream_intf_stream.source c_o,
// output d stream + handshake
hwpe_stream_intf_stream.sink d_i,
// TCDM ports
hwpe_stream_intf_tcdm.master tcdm [MP-1:0],
// control channel
input ctrl_streamer_t ctrl_i,
output flags_streamer_t flags_o
);