Error: a variable index into the generate block 'reg_array' is illegal

SystemVerilog
,
1

Hello,

I have a question particularly related to vsim-3745, trying to exploit a variable index inside a generate loop and fail to do so.

Example code has been attached to this post.

Basically, a couple of shift registers instantiated with the first generate loop, and in the second generate loop, depending on the value of REG_COL_NUM always_ff statement changes. In particular, if REG_COL_NUM > 1 then else statement is activated. With stage_index_ I am hoping to loop over the first dimension of reg_array, but ModelSim complaints about vsim-3745, which is a variable index into the generate block ‘reg_array’ is illegal.

My sutiation is somewhat similar to Niyati’s one, but mine is simpler I think as no tasks/functions need to be called, only trying to assess a particular index of the dimension of reg_array.

Any thoughts would be much appreciated.

Best regards,

    localparam REG_COL_NUM = 1;
    localparam POSSIBLE_REG_NUM [0:1] = `{1, 2};
    localparam PARALLELISM = 2;
    genvar stage_index;
    int stage_index_;
   
    // instantiate a 2-dim array of shift registers
    generate
        for (stage_index=0; stage_index<REG_COL_NUM; stage_index++) begin: reg_array
            reg [PARALLELISM-1:0] reg_col [POSSIBLE_REG_NUM[stage_index]-1:0];        
         end
    endgenerate
    
    generate 
        if (REG_COL_NUM == 1) begin
            always_ff @(posedge clk, negedge nreset) begin
                if (~nreset)         
                    reg_array[0].reg_col[0] <= 0;
                else
                    reg_array[0].reg_col[0] <= wire;    
                end
             end        
         end
        else begin        
            always_ff @(posedge clk, negedge nreset) begin
                if (~nreset) begin
                    for (stage_index_=0; stage_index_<REG_COL_NUM; stage_index_++) begin
                        reg_array[stage_index_].reg_col[0] <= 0;
                     end
                 end
                else begin
                
                    ...

                 end
2

In reply to taihaichen:

The problem/solution is the same as in the other post you mention. The generate-for loop does not create true arrays that can be indexed with a dynamically changing variable. You must use constants or another generate-for loop to access reg_array. I would move the procedural-for loop into a generate for loop.

 for (genvar stage_index_=0; stage_index_<REG_COL_NUM; stage_index_++) begin
     always_ff @(posedge clk, negedge nreset)
                if (~nreset) 
                        reg_array[stage_index_].reg_col[0] <= 0;
                    
  end
3

In reply to dave_59:

In reply to taihaichen:
The problem/solution is the same as in the other post you mention. The generate-for loop does not create true arrays that can be indexed with a dynamically changing variable. You must use constants or another generate-for loop to access reg_array. I would move the procedural-for loop into a generate for loop.

 for (genvar stage_index_=0; stage_index_<REG_COL_NUM; stage_index_++) begin
always_ff @(posedge clk, negedge nreset)
if (~nreset) 
reg_array[stage_index_].reg_col[0] <= 0;
end

Thanks a lot for this Dave. That’s exactly what I am looking for.