Error using Generated instance name in module connection

SystemVerilog
1

Error-[ELAB-ICIP] Illegally connected interface port
…/rtl/top.sv, 154
“i2c_1 Master0(slave_if[0].i2c_s_if);”
The interface port ‘if_port’ of module ‘i2c_1’ whose type
is interface ‘i2c_if’ is illegally connected. An unresolved or
generated instance name ‘slave_if[0].i2c_s_if’ is used.
Please make sure that all ports are properly connected

slave_if is my gen block name

 generate
   for(genvar j=0;j<`NUM_OF_SLAVE_INTERFACES;j++)
begin :slave_if
      
      i2c_if i2c_s_if(clk_i2c1);  // Create multiple instances here

I cant use generated instance names in connections? how do i resolve this?

2

In reply to kranthi445:

Not nearly enough code shown to know what your issue is. What are Master0, i2c_1, clk_2clk?