Error of "non-illegal/ignore user-defined bins" while coding cross coverage?

SystemVerilog
, ,
1

I am trying to achieve a cross coverage between one normal cover point and one already cross-ed set. Using the following code:




    clock_variation : coverpoint cfg.frame_rate {
       bins ideal  = {48000};
       bins p_five = {50400};
       bins m_five = {45600};
     } 

    cross1_freq_and_modes  : cross channel_length,no_of_channels {
       bins f3p072aa = binsof(no_of_channels.t4) && binsof(channel_length.ch16);
       bins f3p072bb = binsof(no_of_channels.t2) && binsof(channel_length.ch32);
     }

    clock_varXosc_clk_freqXtdm_slot_sizeXnum_of_ch : cross cross1_freq_and_modes,clock_variation { 
      bins f3with0percent = binsof(cross1_freq_and_modes.f3p072aa) && binsof(clock_variation.ideal);
      bins f3with5percent = binsof(cross1_freq_and_modes.f3p072aa) && binsof(clock_variation.p_five);
    } //Error here

However I’m getting this error:
The cross ‘cross1_freq_and_modes’ cannot be used in the definition of cross of cross ‘clock_varXosc_clk_freqXtdm_slot_sizeXnum_of_ch’ since non-illegal/ignore user-defined bins are defined in its specification.

How is this so? I haven’t declared any ‘ignore’ bins in ‘cross1_freq_and_modes’ and what exactly is a non-illegal (legal?) bin?

2

In reply to ambreezesj:
You’ll have to ask your tool vendor why you are getting the misleading error message, but it is not legal to define a cross using an existing cross.