Error-[IFRLHS-UAMD] Illegal force/release used on LHS

SystemVerilog
1

Hi all,

I am getting the below error

Error-[IFRLHS-UAMD] Illegal force/release used on LHS
/tmp/netbatch/kenchugx_20200925_205559_itpp_reader_test__model_uncore_at_speed_cap_psf1_npk.spf.itpp/itpp_reader_test__model_uncore_at_speed_cap_psf1_npk.spf.itpp/itpp_reader_test.sv, 272679
Force/Release of an unpacked array which is driven by a mixture of
structural and procedural assignments is not valid.
The offending expression:
soc_tb.soc.par_psf1_npk.psf1_wrap.psf1.i_psf20_top_psf1.i_psf20_top_pgd.i_psf20_top_core.i_pg[0].i_psf20_portgrp.port_assign[0].gen_tt
…
Source info: force
soc_tb.soc.par_psf1_npk.psf1_wrap.psf1.i_psf20_top_psf1.i_psf20_top_pgd.i_psf20_top_core.i_pg[0].i_psf20_portgrp.port_assign[0].gen_ttif_nobuf.i_psf20_t
…

the below signals I am forcing,
force soc_tb.soc.par_psf1_npk.psf1_wrap.psf1.i_psf20_top_psf1.i_psf20_top_pgd.i_psf20_top_core.i_pg[0].i_psf20_portgrp.port_assign[0].gen_ttif_nobuf.i_psf20_ttif_asym_nobuf.agt_target_decoder_visa.decoder_tier1.dest_id[0]=1’bx;
force soc_tb.soc.par_psf1_npk.psf1_wrap.psf1.i_psf20_top_psf1.i_psf20_top_pgd.i_psf20_top_core.i_pg[0].i_psf20_portgrp.port_assign[0].gen_ttif_nobuf.i_psf20_ttif_asym_nobuf.agt_target_decoder_visa.decoder_tier1.dest_id[1]=1’bx;
force soc_tb.soc.par_psf1_npk.psf1_wrap.psf1.i_psf20_top_psf1.i_psf20_top_pgd.i_psf20_top_core.i_pg[0].i_psf20_portgrp.port_assign[0].gen_ttif_nobuf.i_psf20_ttif_asym_nobuf.agt_target_decoder_visa.decoder_tier1.dest_id[2]=1’bx;
force soc_tb.soc.par_psf1_npk.psf1_wrap.psf1.i_psf20_top_psf1.i_psf20_top_pgd.i_psf20_top_core.i_pg[0].i_psf20_portgrp.port_assign[0].gen_ttif_nobuf.i_psf20_ttif_asym_nobuf.agt_target_decoder_visa.decoder_tier1.dest_id[3]=1’bx;
force soc_tb.soc.par_psf1_npk.psf1_wrap.psf1.i_psf20_top_psf1.i_psf20_top_pgd.i_psf20_top_core.i_pg[0].i_psf20_portgrp.port_assign[0].gen_ttif_nobuf.i_psf20_ttif_asym_nobuf.agt_target_decoder_visa.decoder_tier1.dest_id[4]=1’bx;
force soc_tb.soc.par_psf1_npk.psf1_wrap.psf1.i_psf20_top_psf1.i_psf20_top_pgd.i_psf20_top_core.i_pg[0].i_psf20_portgrp.port_assign[0].gen_ttif_nobuf.i_psf20_ttif_asym_nobuf.agt_target_decoder_visa.decoder_tier1.dest_id[5]=1’bx;
force soc_tb.soc.par_psf1_npk.psf1_wrap.psf1.i_psf20_top_psf1.i_psf20_top_pgd.i_psf20_top_core.i_pg[0].i_psf20_portgrp.port_assign[0].gen_ttif_nobuf.i_psf20_ttif_asym_nobuf.agt_target_decoder_visa.decoder_tier1.dest_id[6]=1’bx;

can u pls help me on this issue.

Thanks in advance
Vijay

2

In reply to VK_18:

Your information is very limited. But we can see,

This “decoder_tier1” must be a model, it should have an unpacked array called dest_id, something like this:

bit [15:0] dest_id[8];

And it is “driven by structure and procedure assignment”. And forcing is not allowed.

You can try to change it into

bit [7:0][15:0] dest_id;

and try again.

3

Thanks ridder

soc_tb.soc.par_psf1_npk.psf1_wrap.psf1.i_psf20_top_psf1.i_psf20_top_pgd.i_psf20_top_core.i_pg[0].i_psf20_portgrp.port_assign[0].gen_ttif_nobuf.i_psf20_ttif_asym_nobuf.agt_target_decoder_visa.decoder_tier1.dest_id[0]=1’bx

agt_target_decoder_visa < – It is packed struct type

output decoder_visa_lanes_t agt_target_decoder_visa;

typedef struct packed {
decoder_visa_tier1_t decoder_tier1;
decoder_visa_tier2_t decoder_tier2;
maptargetid_visa_lanes_t maptargetid_tierall;
} decoder_visa_lanes_t;

and inside the agt_target_decoder_visa, the decode_tier1 is also a packed struct type,

typedef struct packed {

logic [DST_ID_WIDTH+2:0] dest_id;
logic usechmap;
logic miss;
logic hit_error;
logic [1:0] trusted_t0_state;

} decoder_visa_tier1_t;

Is there any way or method to force dest_id , without changing the RTL code ?

4

In reply to VK_18:

for the above query, i just wrote a simple verilog code with 2 struct packed data types, there “cc” struct packed is declared in “bb” struct packed data type.

here i am unable to get any error, like above.

module aa;

typedef struct packed {
bit [1:0] u;
bit [1:0] v;
} cc;

//cc cc_1;

typedef struct packed {
cc cc_2;
bit [1:0] v;
} bb;

bb bb_1;

initial begin
force bb_1.cc_2.u[0] = 1’b1;
$display(" bb_1.cc_2.u[0] = %d", bb_1.cc_2.u[0]);
end

endmodule

Output :

Top Level Modules:
aa
TimeScale is 1 ns / 1 ns
Starting vcs inline pass…

1 module and 0 UDP read.
recompiling module aa
rm -f csrc*.so pre_vcsobj.so share_vcsobj_.so
if [ -x …/simv ]; then chmod -x …/simv; fi
g++ -o …/simv -m32 -m32 -rdynamic -Wl,-rpath=‘$ORIGIN’/simv.daidir -Wl,-rpath=./simv.daidir -Wl,-rpath=/apps/vcsmx/vcs/P-2019.06-1/linux/lib -L/apps/vcsmx/vcs/P-2019.06-1/linux/lib -Wl,-rpath-link=./ objs/amcQw_d.o _304_archive_1.so SIM_l.o rmapats_mop.o rmapats.o rmar.o rmar_nd.o rmar_llvm_0_1.o rmar_llvm_0_0.o -lvirsim -lerrorinf -lsnpsmalloc -lvfs -lvcsnew -lsimprofile -luclinative /apps/vcsmx/vcs/P-2019.06-1/linux/lib/vcs_tls.o -Wl,-whole-archive -lvcsucli -Wl,-no-whole-archive /apps/vcsmx/vcs/P-2019.06-1/linux/lib/vcs_save_restore_new.o /apps/vcsmx/vcs/P-2019.06-1/linux/lib/ctype-stubs_32.a -ldl -lc -lm -lpthread -ldl
…/simv up to date
CPU time: .244 seconds to compile + .357 seconds to elab + .292 seconds to link
Chronologic VCS simulator copyright 1991-2019
Contains Synopsys proprietary information.
Compiler version P-2019.06-1; Runtime version P-2019.06-1; Sep 30 23:32 2020
bb_1.cc_2.u[0] = 1
V C S S i m u l a t i o n R e p o r t
Time: 0 ns
CPU Time: 0.540 seconds; Data structure size: 0.0Mb
Wed Sep 30 23:32:42 2020

code link : packed_structure - EDA Playground

can u pls help me on this issue.
thanks in advance