Error on checking assertion for stability of 50 Mhz clock

SystemVerilog
,
1

My intention is to write an assertion for checking whether my clocking stable.
I have wrote the following code:

Its showing error inside property :: check_frquency

module assert_clock;

// Assertion for checking frequency
//Frquency 50 Mhz , time period = 20ns

bit clock;

    default clocking cb_clk @ (posedge clock);

sequence _clockrise(local output byte risetime);
	($rose(clock),risetime=$time);
endsequence : _clockrise

sequence _clock_nextrise(local output byte next_risetime);
	($rose(clock),next_risetime=$time);
endsequence : _clock_nextrise

property _clock(local output byte time_period);
	byte risetime,next_risetime;
	_clockrise(risetime) |-> ( _clock_nextrise(next_risetime), time_period = next_risetime-risetime );
endproperty : _clock

property check_frequency;
	 byte time_period;
	(_clock(time_period), time_perio);
endproperty :check_frequency

CLOCK_FREQUENCY_CHECK : assert property(check_frequency);

initial forever #10 clock=!clock;

initial #200 $finish();
endmodule : assert_clock
2

In reply to bachan21:

Why make life easy when instead you can make it complicated.

Rewrite your property as a single declaration without any sequence declaration.
It will be easier to read and follow.
I’ll look at it then.
What you currently have is hard to follow and the complexity you bring is not warranted.
Ben systemverilog.us