Hello, here are the codes for some system verilog modules for my project. One is the top level module and its test-bench and the last one is the ‘genreg module’ instantiated from the top module.
//top_level.sv//
`define window_size 8 //default windows size (measured in strides)
`define stride_length 32//(256 bits)default stride length (measured in bytes)
module top_level(input clk, input reg [7:0] in, output [$clog2(`stride_length*`window_size)+1:0] output_sum);
//wire [$clog2(`stride_length*`window_size)+1:0] output_sum;
wire match;
wire [$clog2(`stride_length):0] out [(`window_size):0];
wire [$clog2(`stride_length):0] in1;
//reg [7:0] in;
reg clr;
reg tick;
//always @(posedge clk)
//begin
featureMatch matched (match, 8'b11111111, 8'b11111111, in);
featureCount testCounter(clk);
Counter countup (out[`window_size], tick, match, clk);
genreg U (out, in1, tick, clk);
windowsum windowsum1 (output_sum, out[`window_size], out[0], in, tick, clk);
//end
endmodule
//top_level_tb.sv//
`define window_size 8 //default windows size (measured in strides)
`define stride_length 32//(256 bits)default stride length (measured in bytes)
module top_level_tb;
// Inputs
reg clk;
reg [7:0] in;
reg [$clog2(`stride_length*`window_size)+1:0] output_sum;
// Instantiate the Unit Under Test (UUT)
top_level uut (
.clk(clk),
.in(in),
.output_sum(output_sum)
);
initial
begin
// Initialize Inputs
clk = 1'b0;
repeat(1000)
begin
in = $random%1000;
wait(clk);
wait(!clk);
$display("output",,output_sum);
end
end
always @(clk) begin
#10 clk = ~clk;
end
endmodule
// genreg.sv //
`define window_size 8 //default windows size (measured in strides)
`define stride_length 32//(256 bits)default stride length (measured in bytes)
module genreg (output reg [$clog2(`stride_length):0] out, input [$clog2(`stride_length):0] in, input tick, clk);
reg [$clog2(`stride_length):0] arr[(`window_size):0];
assign out = arr[(`window_size)];
assign arr[0] = in;
generate
genvar i;
for (i=1; i <= `window_size; i = i + 1) begin : theRegisters
regs U1 (arr[i], arr[i-1], tick, clk);
end
endgenerate
endmodule
After i compile all the modules all and run the testbench (module 2) it gives an error:
Error :(vsim-3906) /u0/users/9/rpandit2/DSD2/msim_tut/src/top_level.sv(19): Connection type is incompatible with port (out): Can’t mix packed and unpacked types.
Please suggest me some solutions and also point out the errors n the code if possible.