I am writing a reference model for verification purpose.
Design has 32KHz clock. How can i model/use clock in ref model.
I cannot directly use the design’s clk.
Can i send the clk from the design to ref model through mailbox,if so how ? since its a very high frequency clock.
The design code is below:
always @ ( posedge clk or negedge rst_n) begin
if(!rst_n) begin
count <= 2'b00;
end
else begin
count <= count + 2'b1;
end
end
How to model the clk??
Thanks in advance !!
In reply to tejasakulu:
Your question is ambiguous.
I am writing a reference model for verification purpose.
By “reference model”, you mean a scoreboard.
Design has 32KHz clock. How can i model/use clock in ref model.
I cannot directly use the design’s clk.
Can i send the clk from the design to ref model through mailbox,if so how ? since its a very high frequency clock.
Why can’t you use the design system clock?
Are you talking about creating a new clock in your verification environment that is synced to the design clock?
I don’t get that mailbox idea.
Assuming that you have a fast clock in your design, and you want to create a slower synced clock in your scoreboard. Also, assuming that you have access to a fast clock, you can do something like
// scoreboard
bit clk_sc; // period of 100ns
bit fast_clk; // period of 10ns
initial @fast_clk forever #50 clk_sc=!clk_sc;
// clk_sc and fast_clk_sc will line up on the rising and falling edges,
// but at the approapriate delays
// assuming that the modeling of fast_clk is something like forever #5 fast_clk=!fast_clk
Thanks ben for the reply. I cannot use system design’s clock, For example i have a design code like
always @ ( posedge clk or negedge rst_n) begin
if(!rst_n) begin
count <= 2'b00;
end
else begin
count <= count + 2'b1;
end
end
As of now i am doing
forever @(posedge mtb.DUT.clk) begin
if(!mtb.DUT.rst_n) begin
count = 2'b00;
end
else begin
count = count + 2'b1;
end
end
Let me know if this is wrong or in general what guidelines should be considered while modeling Ref Model for scoreboard.
Thanks,
Tejas
Let me know if this is wrong or in general what guidelines should be considered while modeling Ref Model for scoreboard.
What you have is fine. However, I see a difference between “scoreboarding + checking” and assertions. I see scoreboarding for special cases, like the results of signal processing, or something very complex. In my paper SVA in a UVM Class-based Environment https://verificationacademy.com/verification-horizons/february-2013-volume-9-issue-1/SVA-in-a-UVM-Class-based-Environment
I make the following CONCLUSIONS AND RECOMMENDATIONS
Verification consists of several methodologies that work well, particularly when combined in symphony. UVM is a class-based methodology that tends to stress the use of scoreboarding to compare expected results against actual observations. Though the scoreboarding approach solves many verification tasks, SVA provides another complementary approach that works with UVM to speed up the model building process, to support the class-based environment, and to quickly localize errors at the cycle level.
Bottom line, I am not enamored by scoreboards, particularly if they are copies of the RTL.
SVA provides complementary advantages for UVM. This includes the simpler definition of temporal design properties for verification and coverage; the support of covergroup sampling control based on sequence of events; the localized detection of errors and effective debug via on-demand waveform/transaction recording; the control of system level tasks based on sequence of events; and the reporting of errors back to the UVM environment for flow control.
For bus protocol types of verification properties (signal level verification), we recommend SVA at the interfaces instead of using scoreboarding with compare as a verification technique. If a tool supports SystemVerilog checkers (1800-2009 and 2012), use checkers bound to interfaces. Assertion results can be written into the interface variables or class static variables for control and access by the UVM environment. For coverage of temporal properties, use assertions in SV interfaces. For covergroups that require the completion of temporal sequences as the sampling trigger, use SVA sequences that can transfer the sampling triggers to class variables. Use UVM severity levels in all SVA action blocks instead of the SystemVerilog native severity levels. Use SVA immediate assertions to flag unsuccessful randomization and terminate the simulation run.
Consider this example: http://SystemVerilog.us/vf/counter_rtlOK.sv
This is a very weird kind of counter, complex to stress the values and capabilities of assertions: // requirements:
// Loadable counter, reset to 0 if reset_n==0,
// Min count -2, Max count ==5
// This is an activity counter, thus count must change at least
// every 8 cycles
In the model (link above) I used assertions to model the requirements and to veify the RTL.
SVA models can be bound to the RTL in the testbench. SV interfaces are other places to put assertions.
In reply to ben@SystemVerilog.us:
For completion, I am inserting the full model of that counter with very complex requirements to demonstrate the power of assertions instead of using scoreboards that may just emulate the RTL.
/******************************************************************************
* (C) Copyright 2009 <Company Name> All Rights Reserved
*
* MODULE: counter
* DEVICE:
* PROJECT:
* AUTHOR: ben2
* DATE: 2011 12:03:56 PM
*
* ABSTRACT: You can customize the file content form Templates "verilog File"
*
*******************************************************************************/
// requirements:
// Loadable counter, reset to 0 if reset_n==0,
// Min count -2, Max count ==5
// This is an activity counter, thus count must change at least
// every 8 cycles
// module counter_max #(MAX_COUNT=9, MIN_COUNT=2)(
module counter_max (
input logic[3:0] data_in,
input logic ld,
output logic[3:0] counter,
input logic clk, rst_n) ;
import counter_pkg::*;
int cover_count=0;
int fail_count=0;
// ap_P: assert property(@ (posedge clk) P )
// parameter MIN_COUNT=2; // module item parameter
// If use of parameter port list, then can't use defparam
default disable iff !rst_n;
property p_load;
logic[3:0] v_data_in; // local variable to property
(ld && (data_in>= MIN_COUNT && data_in <= MAX_COUNT), v_data_in=data_in) |=>
counter==v_data_in;
endproperty : p_load
ap_load: assert property ( @(posedge clk) p_load);
property p_hold_on_load;
ld && (data_in< MIN_COUNT || data_in > MAX_COUNT) |=>
$stable(counter);
endproperty : p_hold_on_load
ap_hold_on_load: assert property ( @(posedge clk) p_hold_on_load);
ap_count: assert property(@(posedge clk)
!ld && (counter!=MAX_COUNT) |=> counter==$past(counter)+1'b1);
ap_hold: assert property(@(posedge clk)
!ld && counter==MAX_COUNT |=> counter==$past(counter));
mp_min_load: assume property(@(posedge clk)
ld |-> not(data_in<MIN_COUNT));
mp_max_load: assume property(@ (posedge clk)
ld |-> not(data_in > MAX_COUNT))
cover_count++; else fail_count++ ;
ap_statble8: assume property(@(posedge clk)
$stable(counter)|-> ##[1:8] !$stable(counter));
ap_reset: assert property(@ (posedge clk) disable iff (1'b0)
!rst_n |=> counter==MIN_COUNT);
always @(posedge clk) begin : counter1
if(!rst_n) counter <= MIN_COUNT;
else if (ld && data_in >= MIN_COUNT && data_in <= MAX_COUNT)
counter <= data_in;
else if (!ld && counter!=MAX_COUNT) begin : counter2
counter <= counter + 1'b1;
end : counter2
end : counter1
endmodule : counter_max
/******************************************************************************
*
* REVISION HISTORY:
*
*******************************************************************************/
Thanks Ben, I liked your idea of using assertions, Assertions are indeed powerful and catch the design errors at their source thus helps in observe-ability and debug-ability. But however, for a counter i agree we can write complex assertions, how about if there is a requirement where we need to verify the whole RTL using scoreboard with checkers implemented, then there is no option right ? Adding assertions for whole of the RTL will make look code bigger. What is your take on it.
how about if there is a requirement where we need to verify the whole RTL using scoreboard with checkers implemented, then there is no option right? Adding assertions for whole of the RTL will make look code bigger. What is your take on it.
What is a scoreboard with checkers other than a set of assertions (in the English sense, not SVA sense) to attest that the design is correct?
The implementation of that verification mechanism can be done in a variety of ways.
Visual analysis of the waveforms – Outdated now, but valid way back then/
Hardware emulation or breadboard of the design
verification code – scoreboard with checkers, SVA, SVA emulation (see 1) SVA Alternative for Complex Assertions in my signature)
Items like interface protocols are best tested with SVA, an assertion language defines the properties of the design and thru simulation or formal verification checks that the design meets the requirements.
Computational items can also use SVA, even something like a CPU with complex instructions like ADD, Multiply, divide, read, write, and combination of.
I see the use of a scoreboard for complex things like signal processing that performs complex operations on an image (FFT, other filters).
The danger of using a scoreboard is that it tends to mimic the design, hopefully at a higher level if that is possible. It does not address the requirements directly. One could even cheat and copy the RTL, which defeats the purpose. SVA, on the other hand, addresses the requirements and not the implementation, and that brings out a better understanding of the requirements, along with its weaknesses for lack of definitions. Different aspects of the requirements are also addressed with SVA (see my funky counter above).
By the way, even the scoreboard has to meet the requirements, but the angle of approach is the implementation, though at a higher level if possible. SVA targets the requirements directly.
That’s my take.
Ben Cohen http://www.systemverilog.us/ben@systemverilog.us
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