Enumerated type with common member

SystemVerilog
,
1

As a part of a agent, I am implementing multiple state machines.
I have encoded the states of these state machines as enumerated type.
Needless to say, all of them have IDLE state as a common state.

Example,
enum {IDLE, TX_ON, TX_WAIT …} tx_state;
enum {IDLE, RX_ON, RX_WAIT …} rx_state;

Right during the compilation, the compiler complains that the second enumerated type has IDLE which has already been declared. I don’t know if there is a way to get out of this.

2

In reply to verif_learner:

Enum label names exist in the same scope as the enum itself. You’ll need to use TX_IDLE and RX_IDLE similar top what you did with the other names.

3

In reply to verif_learner:

See also A New Twist on SystemVerilog Enumerated Types.

4

In reply to sbellock:

Thanks, Dave and Bellock. I think I understand the issue now.
Probably, the best option in my case would be to simply declare the enumerated type declaration its individual class as these are very class specific and unlikely to be used by anyone else.